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[VHDL编程] Designfiles
说明:deals about video compression technique jpeg format JPED_enc<Vinod Kumar> 在 2025-04-24 上传 | 大小:59kb | 下载:0
[VHDL编程] cfo_correction
说明:OFDM载波同步,Verilog编写,完全正确-verilog<chen> 在 2025-04-24 上传 | 大小:2.28mb | 下载:0
[VHDL编程] Digital.Logic.And.Microprocessor.Design.With.VHDL
说明:Design Processors & Logic in VHDL. Theory & Examples.<Norbert> 在 2025-04-24 上传 | 大小:4.62mb | 下载:0
[VHDL编程] VHDL-Programming-by-Example---Douglas-L.-Perry.zi
说明:Very good e-book of practical design in VHDL (many practical examples).<Norbert> 在 2025-04-24 上传 | 大小:1.77mb | 下载:0
[VHDL编程] signaltapII_verilogDE2
说明:This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in cir<hejianlun> 在 2025-04-24 上传 | 大小:372kb | 下载:0