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[VHDL编程] CourseDesign
说明:用Verilog实现一位原码浮点数乘法器,按照累加的方式,逐位相乘,再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.<李伟彬> 在 2025-02-28 上传 | 大小:240kb | 下载:0
[VHDL编程] xuliejianceqi
说明:序列检测器在数据通信、雷达和遥控领域中用于检测同步识别标志。他是一种用来检测一组或多组序列型号的电路-Sequence detector in data communication, radar and remote areas to detect synchronization marker. He is used to detect one or more types of circuit sequence<冯翔> 在 2025-02-28 上传 | 大小:145kb | 下载:0