资源列表
[VHDL编程] MUX_ise12migration
说明：mux for fpga vhdl code-mux for fpga vhdl code<fifi> 在 2024-11-17 上传 | 大小：46kb | 下载：0
[VHDL编程] qpsk-modulation--achieved-by-Verilog
说明：qpsk的调制解调的Verilog实现,用Verilog语言来编写实现qpsk调制的实现，已经经过仿真通过。-qpsk modem s Verilog implementation using Verilog language to write achieve qpsk modulation implementation has passed through simulation.<daruili> 在 2024-11-17 上传 | 大小：4kb | 下载：0
[VHDL编程] counter-achieved-by-verilog
说明：该代码用Verilog语言实现了计数功能，主要实现29为计数，已通过仿真验证。-The code in Verilog realize the counting function, the main achievement of 29 counts, has been verified by simulation.<daruili> 在 2024-11-17 上传 | 大小：2kb | 下载：0
[VHDL编程] divider-achieved-by-verilog
说明：该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.<daruili> 在 2024-11-17 上传 | 大小：2kb | 下载：0
[VHDL编程] shfiting-output-achieved-by-verilog
说明：该代码用Verilog语言实现了移位输出功能，主要实现对输入信号进行移位输出，已通过仿真验证。-The code in Verilog realize the shift output function, the main achievement of the input signal shift output has been verified by simulation.<daruili> 在 2024-11-17 上传 | 大小：3kb | 下载：0
[VHDL编程] weimafashengqi-achieved-by-verilog
说明：该代码用Verilog语言实现了M序列的伪码产生，伪码特征方程为X13 +X7+X5+1，已通过仿真验证。-The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.<daruili> 在 2024-11-17 上传 | 大小：3kb | 下载：0
[VHDL编程] AlertLogPkg
说明：osvvm alert packages that is helpful for vhdl verification<anupam maurya> 在 2024-11-17 上传 | 大小：13kb | 下载：0