说明:利用Quartus II实现基于Nios的CPU软核设计实现。包括基本原理和实现代码。-Make use of Quartus II realization to design a realization according to the Nios CPU soft pit.Include basic principle and carry out a code.
<mr.liu> 在 2025-03-01 上传
| 大小:455kb | 下载:0
说明:本例设计一个码率为500kb/s,字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。-This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to <mr.liu> 在 2025-03-01 上传
| 大小:95kb | 下载:0
说明:用Verilog实现模拟三层电梯控制,包括上行、下行、停止、开关门等效果。-Using Verilog to realize simulation of three layer elevator control, including the uplink, downlink, stop, switch door effect. <色素> 在 2025-03-01 上传
| 大小:2.69mb | 下载:0
说明:完成FIFO功能:the first element added to a queue will occur in the first place in the queue, the second element added to the queue will be after
the first one-a kind of First-In-First-Out (FIFO) data structure,the first ele <董俊翔> 在 2025-03-01 上传
| 大小:546kb | 下载:0