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[VHDL编程] Challenges-in-the-design-of-frequency-synthesizer
说明:this document discribes the Challenges in the design of frequency synthesizers for wirele-this document discribes the Challenges in the design of frequency synthesizers for wireless<Read/WDX> 在 2025-03-31 上传 | 大小:691kb | 下载:0
[VHDL编程] 5-ge-ram-core
说明:5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人She<YeZiqiang> 在 2025-03-31 上传 | 大小:1.1mb | 下载:0