[VHDL编程] DE2_disc.part2

说明：DE2光盘资料，请把 part1-part3全下载下来，然后放到一起解压，文件太大，-DE2 CD-ROM, please download part1-part3 all down, and then put together with decompression, file is too large,
<Tnavy> 在 2025-02-09 上传 | 大小：62.08mb | 下载：0

[VHDL编程] 11.23

说明：电子音乐盒,实现do re mi的功能.-dianziyinyuehe
<syh> 在 2025-02-09 上传 | 大小：1019kb | 下载：0

[VHDL编程] try2

说明：vhdl与原理图混合的方式进行设计 vhdl语言描述底层模块，再用原理图设计的方法设计顶层原理图文件-vhdl mixed approach with the schematic design vhdl language to describe the bottom of the module, and then designed the schematic design of the top-level schematic fil
<顾婷婷> 在 2025-02-09 上传 | 大小：315kb | 下载：0

[VHDL编程] aescore

说明：基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
<李华> 在 2025-02-09 上传 | 大小：191kb | 下载：0

[VHDL编程] tut_simulation_verilog

说明：This tutorial introduces the basic features of the QuartusII Simulator.
<Nguyen Chi Nhan> 在 2025-02-09 上传 | 大小：294kb | 下载：0

[VHDL编程] SequentialCircuitDesign_withVerilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth
<Nguyen Chi Nhan> 在 2025-02-09 上传 | 大小：292kb | 下载：0

[VHDL编程] tut_quartus_intro_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth
<Nguyen Chi Nhan> 在 2025-02-09 上传 | 大小：800kb | 下载：0

[VHDL编程] tut_timing_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth
<Nguyen Chi Nhan> 在 2025-02-09 上传 | 大小：361kb | 下载：0

[VHDL编程] Verilog_VHDL_Golden_Reference_Guide

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth
<Nguyen Chi Nhan> 在 2025-02-09 上传 | 大小：272kb | 下载：0

[VHDL编程] Crack_Altera_Quartus61.0-9.1

说明：Crack_Altera_Quartus61.0-9.1.rar license-Crack_Altera_Quartus61.0-9.1.rar license!!!
<guobo> 在 2025-02-09 上传 | 大小：257kb | 下载：0

[VHDL编程] 80C51_1

说明：1.异步通信软件模拟2.基于RS-232的串口通信3.基于RS-485的多机通信4. I2C总线协议的软件实现5. SPI总线在单片机系统中的实现6.-wire-1. Asynchronous communication software simulation 2. Based on the RS-232 serial communication 3. Based on the RS-485 Multi-machine communic
<hdm> 在 2025-02-09 上传 | 大小：63kb | 下载：0

[VHDL编程] keyscan

说明：2×8 键盘扫描编程--- VHDL语言-2×8 keyboard scan---VHDL language
<rjy> 在 2025-02-09 上传 | 大小：1kb | 下载：0