资源列表
[VHDL编程] digital_lock
说明:Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by press<deepa> 在 2025-02-03 上传 | 大小:7kb | 下载:0
[VHDL编程] Traffic_llight_controller
说明:Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. T<deepa> 在 2025-02-03 上传 | 大小:6kb | 下载:0
[VHDL编程] request_arbiter
说明:// Inputs --- // DMACSREQ_i -- The 16-bit signal which stores the single request of all the 16 devices // DMACBREQ_i -- The 16-bit signal which stores the burst request of all the 16 devices // hclk_i -- Clock sig<deepa> 在 2025-02-03 上传 | 大小:11kb | 下载:0
[VHDL编程] ad9777_ini
说明:Verilog编写的AD9777初始化代码-Verilog code to initialize the preparation of the AD9777<hanpei> 在 2025-02-03 上传 | 大小:1kb | 下载:0
[VHDL编程] arithmetic
说明:在Verilog环境下实现简单的数学逻辑运算从而更好的了解 VHDL的编程风格-arithmetic<蓝天> 在 2025-02-03 上传 | 大小:56kb | 下载:0