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[VHDL编程] snake
说明:Gradient Vector Flow (GVF) snake is one kind of active contours - curves that can move within images to find the boundaries of objects. 3D active contours are also known as deformable models. GVF snake begins with calcul<jeffsantana > 在 2024-11-12 上传 | 大小:227kb | 下载:0
[VHDL编程] sdram controller
说明:Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provi<Robuster > 在 2024-11-12 上传 | 大小:8kb | 下载:1
[VHDL编程] New folder
说明:clock div testbench design and frquency division<Bharadwaj > 在 2024-11-12 上传 | 大小:3kb | 下载:0
[VHDL编程] Verilog HDL program
说明:文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法,介绍了Modelsim,chipscope,textbench等仿真方法,并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and<没伞的孩子 > 在 2024-11-12 上传 | 大小:11.03mb | 下载:0
[VHDL编程] encoder_clk
说明:精确实现奇数分频,将FPGA开发板提供的25MHZ时钟分频为1MHZ,内含测试文件(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)<没伞的孩子 > 在 2024-11-12 上传 | 大小:528kb | 下载:0