资源列表
[VHDL编程] Tristate-buffers
说明:本程序完成三态缓冲器的功能,采用硬件编程语言VHDL实现。-This procedure completion tristate buffers using hardware programming language VHDL implementation.<杨好人> 在 2024-11-14 上传 | 大小:19kb | 下载:0
[VHDL编程] multichannel-selector
说明:本程序实现了二选一多路选择器的硬件功能,采用VHDL语言编写而成。-This program implements a second election multiplexer hardware function, written in VHDL language.<杨好人> 在 2024-11-14 上传 | 大小:21kb | 下载:0
[VHDL编程] Serial-borrow-eight-subtracte
说明:本程序实现了串行借位的八位减法器,采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.<杨好人> 在 2024-11-14 上传 | 大小:25kb | 下载:0
[VHDL编程] Digital-clock
说明:利用Quartus编程软件及EDA实验板(芯片为EP1C6Q240C8)完成数字钟设计,该数字钟有显示时、分和秒的功能。-When the Quartus programming software and EDA experiment board (chip EP1C6Q240C8) complete digital clock, digital clock showing the hours, minutes and seconds<杨好人> 在 2024-11-14 上传 | 大小:91kb | 下载:0
[VHDL编程] controller
说明: Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyrig<mohamed> 在 2024-11-14 上传 | 大小:2kb | 下载:0
[VHDL编程] Controller(FSM)
说明: Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using<mohamed> 在 2024-11-14 上传 | 大小:2kb | 下载:0
[VHDL编程] GCD-CALCULATOR
说明: GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataP<mohamed> 在 2024-11-14 上传 | 大小:2kb | 下载:0