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[VHDL编程action_vip_uart

说明:FPGA串口使用程序,通过调试验证,直接调用即可,方便使用-FPGA UART
<tangping> 在 2024-11-20 上传 | 大小:808kb | 下载:0

[VHDL编程fifo

说明:CAN总线,DSP+FPGA+SJA1000架构,FPGA负责逻辑设计,此文件内有FPGA负责dsp和sja1000通信-CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
<张浩阳> 在 2024-11-20 上传 | 大小:4kb | 下载:0

[VHDL编程control_logic

说明:PCI总线的状态机程序,用突发模式写的,单周期可以用,突发模式没驱动,很好的东西哦-PCI bus state machine programs written using burst mode, single-cycle can be used, no burst mode driver, a very good thing, oh
<张浩阳> 在 2024-11-20 上传 | 大小:2kb | 下载:0

[VHDL编程uart_send

说明:串口发送程序,用无数设备验证过的,可靠,波特率2M,系统时钟40M-Serial transmission program, verified by numerous equipment, reliable baud 2M, the system clock 40M
<张浩阳> 在 2024-11-20 上传 | 大小:1kb | 下载:0

[VHDL编程24bit-dadda-multiplier

说明:IT IS HIGHBRID MULTIPLIER WHERE WILL BE USEFUL TO GET HIGH SPEED MULTIPLICATION IN PROCESSORS
<ajay kumar> 在 2024-11-20 上传 | 大小:8kb | 下载:0

[VHDL编程reversible-squarer

说明:it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
<ajay kumar> 在 2024-11-20 上传 | 大小:2kb | 下载:0

[VHDL编程ddfs

说明:IT IS THE CIRCUIT WHICH EXACTLY WORK AS SINE WAVE GENERATOR, THIS CAN BE EFFICIENTLY USED IN THE COMMUNICATIONS SYSTEMS
<ajay kumar> 在 2024-11-20 上传 | 大小:87kb | 下载:0

[VHDL编程4-2-compressor

说明:IT IS THE HYBRID COMPRESSOR WHICH WILL BE USEFUL LOW POWER SINCE THE GATE COUNT AND DELAY REQUIRED IS VERY LESS COMPARED TO THE NORMAL DESIGN
<ajay kumar> 在 2024-11-20 上传 | 大小:1.53mb | 下载:0

[VHDL编程vid_clkgen

说明:Xilinx xapp sink displayport vid clk geneator source
<asdfqqqwa> 在 2024-11-20 上传 | 大小:1kb | 下载:0

[VHDL编程submicron-technology

说明:IT IS THE TECHNOLOGY TO REDUCE THE SHORT CIRCUIT LEKAGE POWER IN CMOS TECHNOLOGY. BY THIS WE CAN AVOID THE SHORT CIRCUIT POWER
<ajay kumar> 在 2024-11-20 上传 | 大小:7kb | 下载:0

[VHDL编程image-rotation

说明:基于FPGA的system generator的图像旋转处理,利用system generator的图像旋转处理程序。本程序是基于system generator下的matlab运行。-FPGA-based image processing system generator rotation, the use of image rotation system generator handler. This procedure is ba
<wyj> 在 2024-11-20 上传 | 大小:155kb | 下载:0

[VHDL编程SRC

说明:流水线CPU的verilog实现,包含id,if,ex,mem等部分的源码-an implementation of Pipelined CPU in verilog
<zyh> 在 2024-11-20 上传 | 大小:7kb | 下载:0
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