资源列表
[VHDL编程] clockdiv_teste
说明:Clock division program write in Verilog with selected divider (32 bits)<rafaelmanfrin> 在 2025-05-01 上传 | 大小:577kb | 下载:0
[VHDL编程] dds(9854)_test(sin_cos)(EP1C6)
说明:通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号,实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.<yanghang> 在 2025-05-01 上传 | 大小:118kb | 下载:0
[VHDL编程] demand-number
说明:检测一个正弦波峰值个数,大于某个固定值时报警。-Detection of a sine wave peak number, greater than a fixed value alarm.<henry> 在 2025-05-01 上传 | 大小:292kb | 下载:0
[VHDL编程] LCD-controller---VHDL
说明:vhdl languge, i use the vhdl language for lcd controller with de2 board.<Nghia> 在 2025-05-01 上传 | 大小:524kb | 下载:0
[VHDL编程] LCD-controller---Nghia
说明:different code for lcd controller using de2 board with vhdl lanuage<Nghia> 在 2025-05-01 上传 | 大小:667kb | 下载:0
[VHDL编程] code-pour-decim-poly
说明:this code is for a decimation filter with polyphase structure , so the original filter is decomposed by 5 filters which is the decimation factor in that case and each of them is selected each Fs/5<lassana> 在 2025-05-01 上传 | 大小:23kb | 下载:0