资源列表
[VHDL编程] vga-veriloghdl
说明:用Verilog HDL编写的VGA显示驱动程序-大家共同学习-Prepared using Verilog HDL VGA display driver- we learn together<> 在 2025-01-31 上传 | 大小:139kb | 下载:0
[VHDL编程] 1.-VHDL-Code-For-BCD-To-Decimal-Decoder-By-Data-F
说明:1. VHDL Code For BCD To Decimal Decoder By Data Flow Modelling<rik> 在 2025-01-31 上传 | 大小:44kb | 下载:0
[VHDL编程] VHDL-Code-For-Full-Subtractor-By-Data-Flow-Modell
说明:VHDL Code For Full Subtractor By Data Flow Modelling<rik> 在 2025-01-31 上传 | 大小:44kb | 下载:0
[VHDL编程] VHDL-Code-For-Half-Subtractor-By-Data-Flow-Modell
说明:VHDL Code For Half Subtractor By Data Flow Modelling<rik> 在 2025-01-31 上传 | 大小:38kb | 下载:0
[VHDL编程] VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling.z
说明:VHDL Code For Full Adder By Data Flow Modelling<rik> 在 2025-01-31 上传 | 大小:32kb | 下载:0
[VHDL编程] VHDL-Code-For-Half-Adder-By-Data-Flow-Modeling.zi
说明:VHDL Code For Half Adder By Data Flow Modeling<rik> 在 2025-01-31 上传 | 大小:28kb | 下载:0
[VHDL编程] VHDL-Code-For-BCD-To-Excess3--Code-Converter-By-D
说明:VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling-VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling<rik> 在 2025-01-31 上传 | 大小:38kb | 下载:0
[VHDL编程] VERILOG_FAQ
说明:Verilog FAQ ------------ This document contains 97 frequently asked questions and their answers related to Verilog. It s for novice to Verilog. But it also useful for intermediate Verilog programmer.<kkk> 在 2025-01-31 上传 | 大小:213kb | 下载:0
[VHDL编程] traffic_light
说明:基于VHDL语言的关于交通路灯的设计,实现现实生活中路*通灯控制-Based on the traffic lights VHDL language design, implementation, real-life intersection traffic light control<yehnan> 在 2025-01-31 上传 | 大小:84kb | 下载:0