搜索资源列表
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus networ
USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
linux-2.4.20-rtl
- 该文件是rt_linux，实现linux的实时功能-rt_linux the document is to achieve real-time functional linux
equlizer
- 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to wri
TabStrip_src
- A TabControl in the Visual Studio 2005 style, which supports correct Right-To-Left (RTL) and Left-To-Right (LTR) drawing-A TabControl in the Visual Studio 2005 STYL e, which supports correct Right-To-Left (RTL) an d Left
RTL
- HMI产品上使用的将黑白屏提升分辨率变为彩色屏的verilog RTL code-verilog RTL code for convert Black/White HMI to high resolution color
RTL
- UART 具有rtl ,实验测试可用，已用于实际工程中-UART has rtl, experimental tests are available, it has been used in the actual project
rtl
- Register Transfer Language (RTL) definitions for GCC.Value used by some passes to recognize noop moves as valid. -Register Transfer Language (RTL) definitions for GCC.Value used by some passes to recognize noop moves
RTL-ARM_-_RTX_Kernel
- RTL-ARM_-_RTX_Kernel实时操作系统内核的使用，可以作为RTX_Kernel的学习资料。-RTL-ARM _-_ RTX_Kernel use of real-time operating system kernel, as RTX_Kernel learning materials.
rtl
- SPI verilog RTL code
rtl
- RTL special definitions for ring0 & ring3 in one header.
rtl
- RTL special definitions for ring0 & ring3 in one header.
BCH-rtl-sourcecode
- BCH RTL 源代码，内容包括解码和编码，适合应用在需要纠错的芯片产品，已经在实际的芯片验证-BCH RTL Source Code, include encode and decode, verified in actual silicon
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
bnr
- 商业化高端视频画质芯片中的deblocking部分的RTL实现结构，实际工程的图。算法方面基本都是一样的。 同时可以把dnr一起在这里边同时做(deblocking rtl architecture for video processing)
rtlsdr_fm_discrim_demod_matlab
- Matlab 软件无线电 RTL-SDR FM解调。。。。。。。。。。。。(This scr ipt can be used to non-coherently demodulate an FM signal. The DSP operations carried out here are identical to those in the "rtlsdr_rx_fm_mono_bbox.slx" Simuli
Verilog数字系统设计
- verilog 数字系统设计 -RTL综合 测试平台与验证 的 随书光盘源程序(This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design)
MATLAB RTL-SDR + code
- Software Defined Radio using MATLAB Simulink and the RTL-SDR + Matlab code