文件名称:FPGA-clock
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基于VHDL的时钟设计（de2开发平台），内含源代码，各模块的时序仿真图，结构原理图，以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
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下载文件列表
FPGA-clock\clock-report.doc
..........\jaymakenew\db\jaymake.db_info
..........\..........\..\jaymake.eco.cdb
..........\..........\..\jaymake.sim.vwf
..........\..........\..\jaymake.sld_design_entry.sci
..........\..........\..\wed.zsf
..........\..........\decoder9.bsf
..........\..........\divide50m.bsf
..........\..........\divide50m.vhd
..........\..........\jaymake.asm.rpt
..........\..........\jaymake.bsf
..........\..........\jaymake.done
..........\..........\jaymake.dpf
..........\..........\jaymake.fit.rpt
..........\..........\jaymake.fit.smsg
..........\..........\jaymake.fit.summary
..........\..........\jaymake.flow.rpt
..........\..........\jaymake.map.rpt
..........\..........\jaymake.map.summary
..........\..........\jaymake.pin
..........\..........\jaymake.pof
..........\..........\jaymake.qpf
..........\..........\jaymake.qsf
..........\..........\jaymake.qws
..........\..........\jaymake.sim.rpt
..........\..........\jaymake.sof
..........\..........\jaymake.tan.rpt
..........\..........\jaymake.tan.summary
..........\..........\jaymake.vhd
..........\..........\jaymake.vwf
..........\..........\jaymake_assignment_defaults.qdf
..........\..........\timer.bsf
..........\..........\db
..........\jaymakenew
FPGA-clock
..........\jaymakenew\db\jaymake.db_info
..........\..........\..\jaymake.eco.cdb
..........\..........\..\jaymake.sim.vwf
..........\..........\..\jaymake.sld_design_entry.sci
..........\..........\..\wed.zsf
..........\..........\decoder9.bsf
..........\..........\divide50m.bsf
..........\..........\divide50m.vhd
..........\..........\jaymake.asm.rpt
..........\..........\jaymake.bsf
..........\..........\jaymake.done
..........\..........\jaymake.dpf
..........\..........\jaymake.fit.rpt
..........\..........\jaymake.fit.smsg
..........\..........\jaymake.fit.summary
..........\..........\jaymake.flow.rpt
..........\..........\jaymake.map.rpt
..........\..........\jaymake.map.summary
..........\..........\jaymake.pin
..........\..........\jaymake.pof
..........\..........\jaymake.qpf
..........\..........\jaymake.qsf
..........\..........\jaymake.qws
..........\..........\jaymake.sim.rpt
..........\..........\jaymake.sof
..........\..........\jaymake.tan.rpt
..........\..........\jaymake.tan.summary
..........\..........\jaymake.vhd
..........\..........\jaymake.vwf
..........\..........\jaymake_assignment_defaults.qdf
..........\..........\timer.bsf
..........\..........\db
..........\jaymakenew
FPGA-clock