文件名称:RISC_CPU
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1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。
在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备
对总线写操作时，在第3.5个时钟周期处，建立写的地址，第4个时钟周期输出数据，第5个时钟周期输出写信号。至第6个时钟结束，第7.5时钟地址输出PC地址，为下一个指令周期做好准备。
2. 操作过程：新建工程，编译compile all，然后仿真，在wave窗口加入要观察的信号，然后run –all，结束时完成test1的测试，重复两次run –all完成test2，test3的波形仿真。
-1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction.
When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction
The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle.
Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the
在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备
对总线写操作时，在第3.5个时钟周期处，建立写的地址，第4个时钟周期输出数据，第5个时钟周期输出写信号。至第6个时钟结束，第7.5时钟地址输出PC地址，为下一个指令周期做好准备。
2. 操作过程：新建工程，编译compile all，然后仿真，在wave窗口加入要观察的信号，然后run –all，结束时完成test1的测试，重复两次run –all完成test2，test3的波形仿真。
-1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction.
When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction
The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle.
Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the
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下载文件列表
RISC_CPU
........\accum.v
........\accum.v.bak
........\addr_decode.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.cr.mti
........\cpu.mpf
........\cpu.v
........\cputop.v
........\datactl.v
........\machine.v
........\machinectl.v
........\ram.v
........\register.v
........\RISC_CPU报告_修改_田连泉.docx
........\rom.v
........\test1.dat
........\test1.JPG
........\test1.pro
........\test1_w.JPG
........\test2.dat
........\test2.JPG
........\test2.pro
........\test2_w.JPG
........\test3.dat
........\test3.JPG
........\test3.pro
........\test3_w.JPG
........\transcript
........\vsim.wlf
........\work
........\....\accum
........\....\.....\verilog.prw
........\....\.....\verilog.psm
........\....\.....\_primary.dat
........\....\.....\_primary.dbs
........\....\.....\_primary.vhd
........\....\addr_decode
........\....\...........\verilog.prw
........\....\...........\verilog.psm
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\adr
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\alu
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\clk_gen
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\counter
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\cpu
........\....\cputop
........\....\......\verilog.prw
........\....\......\verilog.psm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\datactl
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machine
........\....\machinectl
........\....\..........\verilog.prw
........\....\..........\verilog.psm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd