文件名称:RISC_cpu
介绍说明－－下载内容均来自于网络，请自行研究使用
基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RISC_cpu\accum.v
........\addr_decode.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.cr.mti
........\cpu.mpf
........\cpu.v
........\datactl.v
........\machine.v
........\machinectl.v
........\register.v
........\test1.dat
........\test1.pro
........\test2.dat
........\test2.pro
........\test3.dat
........\test3.pro
........\test_cpu.v
........\transcript
........\vsim.wlf
........\work\accum\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\.ddr_decode\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\..r\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.lu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\clk_gen\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.ounter\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.pu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\datactl\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\machine\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.......ctl\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\ram\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.egister\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\.om\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\test_cpu\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\_info
........\仿真部分波形.jpg
........\测试结果.txt
........\综合报告.txt
........\网表文件.v
........\覆盖率报告.txt
........\work\accum
........\....\addr_decode
........\....\adr
........\....\alu
........\....\clk_gen
........\....\counter
........\....\cpu
........\....\datactl
........\....\machine
........\....\machinectl
........\....\ram
........\....\register
........\....\rom
........\....\test_cpu
........\....\_temp
........\work
RISC_cpu
........\addr_decode.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.cr.mti
........\cpu.mpf
........\cpu.v
........\datactl.v
........\machine.v
........\machinectl.v
........\register.v
........\test1.dat
........\test1.pro
........\test2.dat
........\test2.pro
........\test3.dat
........\test3.pro
........\test_cpu.v
........\transcript
........\vsim.wlf
........\work\accum\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\.ddr_decode\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\..r\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.lu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\clk_gen\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.ounter\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.pu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\datactl\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\machine\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.......ctl\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\ram\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.egister\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\.om\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\test_cpu\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\_info
........\仿真部分波形.jpg
........\测试结果.txt
........\综合报告.txt
........\网表文件.v
........\覆盖率报告.txt
........\work\accum
........\....\addr_decode
........\....\adr
........\....\alu
........\....\clk_gen
........\....\counter
........\....\cpu
........\....\datactl
........\....\machine
........\....\machinectl
........\....\ram
........\....\register
........\....\rom
........\....\test_cpu
........\....\_temp
........\work
RISC_cpu