文件名称:dividers
- 所属分类:
- VHDL编程
- 资源属性:
- [VHDL] [源码]
- 上传时间:
- 2012-11-26
- 文件大小:
- 10kb
- 下载次数:
- 0次
- 提 供 者:
- miss *****
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
verilog格式的除法器,试过了,很好用,再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dividers
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\verilog
........\.....\.......\bench_div_top.v
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\timescale.v
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\verilog
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\div.v
........\...\.......\div_su.v
........\...\.......\div_us.v
........\...\.......\div_uu.v
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\verilog
........\.....\.......\bench_div_top.v
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\timescale.v
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\verilog
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\div.v
........\...\.......\div_su.v
........\...\.......\div_us.v
........\...\.......\div_uu.v