搜索资源列表
UART
- 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
FPGA0
- FPGA的单片机多机串行通信网络。本文提及的大尺寸数码管动态驱动和保护电路-FPGA-MCU Multi-machine serial communications network. Mentioned in this large size digital tube dynamic drive and protection circuits
FPGA0
- SRAM读写时序，先读入一串数据，然后再实现输出-SRAM write and read
fpga0
- 哈工大计算机设计与实验的其中一个实验，测试实验仪器用的VHDL代码-HIT computer design and experiment in which an experiment, test laboratory instruments used in VHDL code