文件名称:UART
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 279kb
- 下载次数：
- 0次
- 提 供 者：
- g***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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介绍说明－－下载内容均来自于网络，请自行研究使用
主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
相关搜索： uart
verilog
ACTEL
verilog
uart
uart
actel
verilog
verilog
uart
actel
actel
fpga0
ACTEL
Verilog
A3P030CN
actel
uart
verilog
actel
相关搜索： uart
verilog
ACTEL
verilog
uart
uart
actel
verilog
verilog
uart
actel
actel
fpga0
ACTEL
Verilog
A3P030CN
actel
uart
verilog
actel
(系统自动生成,下载前可以参看下载内容)
下载文件列表
component
constraint
coreconsole
designer
........\impl1
........\.....\designer.log
........\.....\simulation
........\.....\uart_test.adb
........\.....\uart_test.dtf
........\.....\.............\verify.log
........\.....\uart_test.ide_des
........\.....\uart_test.pdb
........\.....\uart_test.pdb.depends
........\.....\uart_test.tcl
........\.....\uart_test_fp
........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
........\.....\............\projectData
........\.....\............\...........\uart_test.pdb
........\.....\............\uart_test.log
........\.....\............\uart_test.pro
hdl
...\rec.v
...\send.v
...\uart_test.v
phy_synthesis
simulation
..........\modelsim.ini
..........\modelsim.ini.sav
smartgen
........\smartgen.aws
stimulus
synthesis
.........\.recordref
.........\backup
.........\......\uart_test.srr
.........\coreip
.........\run_options.txt
.........\stdout.log
.........\syntmp
.........\......\sap.log
.........\......\uart_test.msg
.........\......\uart_test.plg
.........\......\uart_test_flink.htm
.........\......\uart_test_srr.htm
.........\......\uart_test_toc.htm
.........\traplog.tlg
.........\uart_test.areasrr
.........\uart_test.edn
.........\uart_test.fse
.........\uart_test.htm
.........\uart_test.map
.........\uart_test.sap
.........\uart_test.sdf
.........\uart_test.so
.........\uart_test.srd
.........\uart_test.srm
.........\uart_test.srr
.........\uart_test.srs
.........\uart_test.tlg
.........\uart_test_sdc.sdc
.........\uart_test_syn.prj
UART.prj
viewdraw
........\sch
........\sym
........\vf
........\..\project.lst
........\viewdraw.ini
........\wir
constraint
coreconsole
designer
........\impl1
........\.....\designer.log
........\.....\simulation
........\.....\uart_test.adb
........\.....\uart_test.dtf
........\.....\.............\verify.log
........\.....\uart_test.ide_des
........\.....\uart_test.pdb
........\.....\uart_test.pdb.depends
........\.....\uart_test.tcl
........\.....\uart_test_fp
........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
........\.....\............\projectData
........\.....\............\...........\uart_test.pdb
........\.....\............\uart_test.log
........\.....\............\uart_test.pro
hdl
...\rec.v
...\send.v
...\uart_test.v
phy_synthesis
simulation
..........\modelsim.ini
..........\modelsim.ini.sav
smartgen
........\smartgen.aws
stimulus
synthesis
.........\.recordref
.........\backup
.........\......\uart_test.srr
.........\coreip
.........\run_options.txt
.........\stdout.log
.........\syntmp
.........\......\sap.log
.........\......\uart_test.msg
.........\......\uart_test.plg
.........\......\uart_test_flink.htm
.........\......\uart_test_srr.htm
.........\......\uart_test_toc.htm
.........\traplog.tlg
.........\uart_test.areasrr
.........\uart_test.edn
.........\uart_test.fse
.........\uart_test.htm
.........\uart_test.map
.........\uart_test.sap
.........\uart_test.sdf
.........\uart_test.so
.........\uart_test.srd
.........\uart_test.srm
.........\uart_test.srr
.........\uart_test.srs
.........\uart_test.tlg
.........\uart_test_sdc.sdc
.........\uart_test_syn.prj
UART.prj
viewdraw
........\sch
........\sym
........\vf
........\..\project.lst
........\viewdraw.ini
........\wir