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rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
RTL-lwIP-0.6
- RTL-lwIP is the porting of the lwIP TCP/IP stack to RTLinux-GPL.The focus of the RTL-lwIP stack is to reduce memory usage and code size, making RTL-lwIP suitable for use in small clients with very limited resources
RTL-Implementation-Guide
- 想做一个合格的ic工程师么？这个文档告诉你怎样写高质量的rtl代码。这是SYNOPSYS注册用户才可下载的文档
rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci-- rtl level.
RTL-lwIP-0.6
- RTL-lwIP is the porting of the lwIP TCP/IP stack to RTLinux-GPL.The focus of the RTL-lwIP stack is to reduce memory usage and code size, making RTL-lwIP suitable for use in small clients with very limited resources
rgb2yuv
- verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。-Verilog prepared, rtl style, pipeline design, realize image rgb to yuv format format conversion.
pci_express_crc
- PCI express CRC rtl core for Fpga/asic Designer
RTL-Implementation-Guide
- 想做一个合格的ic工程师么？这个文档告诉你怎样写高质量的rtl代码。这是SYNOPSYS注册用户才可下载的文档-Want a qualified engineer ic it? This document tell you how to write high quality code rtl. This is the Synopsys registered users can download the document
rl_arm_rtl_rtx_artx
- KEIL自带操作系统RTL的中文帮助文档,很全面.-KEIL own operating system, the Chinese RTL help document, very comprehensive.
rtl
- DDR控制器 已通过FPGA 验证 大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
USBHost+gba_nds_fat
- 看到最近大家都关心 usbhost 的实现, 论坛上能找到的代码仅是一些简单的 demo , 完整的源码级的协议层是找不到的 我就贡献一把, 将我前一段时间移植成功的 USBHost 代码奉上 注意事项 1. ohci 层移植自 u-boot-1.3.2-rc3 2. fat 层移植自 gba_nds_fat 3. 本代码只是我产品中的一部分, 使用 Keil RTL 操作系统, 任务为 void task_usb(
RTL-lwIP-0.6
- 经典的TCP/IP协议栈，非常适合于开发者从代码的角度来理解tcp/ip的原理-The classic TCP/IP protocol stack, very suitable for development from the perspective of the code to understand tcp/ip Principle
verificationOfSLMandRTL
- Design for Verification in System-level Models and RTL, very good and classic
rtl
- SPI verilog RTL code
Describing-Synthesizable-RTL-in-SystemC
- Describing Synthesizable RTL in SystemC
can-rtl
- can 网络通讯问题的解决 加上rtl多任务-network communication problems can
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.A
- Wiley IEEE PRESS RTL Hardware Design using VHDL 2006
Principles-of-Verifiable-RTL-Design
- RTL设计的基本方法，帮助掌握RTL编码方法-RTL
FastMM-RTL
- Delphi7 FastMM RTL 补丁, 其主要目的就是重新实现一个高效、安全、稳定的内存管理器-Delphi7 FastMM RTL