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quartusii9.1_handbook
- quartusii9.1_handbook用户手册吗，是最新版的altera fpga开发软件资料，altera官方资料，是学习altera fpga的必备资料，（全英文版）中文版我会尽快上传-quartusii9.1_handbook user manual you, is the latest version of the altera fpga software development information, altera of
nios_shi
- 由nios ii实现的，用cfi flash与SDRAM共同实现的电子数字时钟，基于sopc的嵌入式代码，所用软件都是9.0版本的，包括quartus ii9.0 和nios ii9.0-Achieved by the nios ii, together with the cfi flash with SDRAM to achieve the electronic digital clock, based on sopc embedde
fadder32
- 短代码实现32位全加器，带经Quartus II9.1编程测试全部文件-Short code to achieve 32-bit full adder, with programming tested by the Quartus II9.1 all documents
fir
- 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
fpga_assignment1
- 这是由简单串行转并行的一个verlog程序，还带testbench，有一张仿真的图片在里面。软件用的是Quartus II9.1 Web Edition。-This is from the simple serial turn a verlog parallel programs, but also bring testbench, and a simulation pictures in it. Software is used II
110819_1
- 基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0-Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0
Quaters--pojie
- 这是QUARTUS ii9.0 的破解包具体破解过程 网上有自己找。
SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
ModelSim6.5bKeyGen
- ModelSim6.5b破解器。配合quartus ii9.1的官网ModelSim破解，已使用，确认正确-ModelSim6.5b Cracking unit。Proved right！
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment fo
new_project
- 本设计是一种基于FPGA的自动售货机控制系统设计。该设计采用FPGA作为主控，设计自动售货机控制系统。模拟实现自动售货机的货物信息存储、货物的选择与购买、金额收取、余额计算、自动找零、状态显示等功能。 采用ALTERA芯片，QUARRTUS II9.1软件，vhdl描述语言进行设计，并通过modelsim进行仿真，最终验证表明，采用FPGA设计，可以更高效，更稳定，更便捷的实现自动售货机功-This design is a vend
ARINC_429
- FPGA实现ARINC429协议，利用verilog HDL做了完整的ARINC429通信收发协议，EDA开发平台为quartus ii9.1。-FPGA implementation ARINC429 protocol using verilog HDL to do a complete ARINC429 communication transceiver protocol, EDA development platform quar