搜索资源列表
13-310010_FSM
- 10010序列检测，用状态机来实现，非常方便-10010 Sequence Detection using the state machine to achieve very convenient
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 outp
13-310010_FSM
- 10010序列检测，用状态机来实现，非常方便-10010 Sequence Detection using the state machine to achieve very convenient
XLJC
- 用状态机实现串行序列检测器的设计 若检测到串行序列11010则输出为1 否则输出为0 并对其进行仿真和硬件测试-State machine used to achieve serial sequence detector designed to detect if the serial sequence 11010 output to 1 otherwise the output is 0 and its simulation and
peak
- 功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Function is to detect a 5 binary sequence
xuliejiancesheji
- 用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0； -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0
seqdet2
- 状态机实现序列检测VerilogHDL及其仿真-State machine implementation sequence VerilogHDL Detect and Simulation
xu_lie_jian_ce_qi
- 本设计通过Moore状态机设计一序列检测计。当输入的序列含有预置的11100101序列中的正确顺序时，进入下一个状态，直到到达st8状态，一个序列检测完毕。值得注意的是，当输入为111100101时，检测计仍能检测出里面的11100101序列，同时，当一个序列检测完毕时，下一个序列的高位可以只含有两个11即输入为1100101时，检测计一样能检测一个正确的序列。-The design by Moore state machine to
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial seque
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequenc
detector
- vhdl语言写的状态机，完成序列检测的功能，包含代码和仿真图-VHDL language used to write the state machine, complete sequence detection features, including code and simulation Figure
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
1111-Sequence-Detection
- 1111序列检测的设计VHDL代码，用状态机实现111序列检测的设计，如果检测到正确的序列，则led灯亮起，否则熄灭-1111 Sequence Detection design VHDL code, using the state machine to achieve 111 Sequence Detection design, if it detects the correct sequence, led lights, other
serial_number_check
- 序列检测，学习verilog三段式状态机的经典例程，modelsim仿真无误-Sequence Detection, three-state machine learning verilog classic routines, modelsim simulation is correct
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document
sequence_detector
- verilog之序列检测，vivado工程，使用状态机的方式检测任意长度的数据顺序，提供四个检测工程，并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides fou
XuLie
- 序列检测机，可检测8位数字序列，米勒型状态机-Sequence detector can detect 8-digit sequence, Miller-type state machine
design
- 使用有限状态机完成序列检测，是FPGA开发中的基础程序(sequence detection with state mation)
class8_FSM
- 序列检测机（状态机实验），是Verilog状态机最基本的小实验，用于体会状态机的原理和作用（原作者：小梅哥）(Sequence detection machine is the most basic small experiment of Verilog state machine)
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are desi