文件名称:VHDL_Development_Board_Sources
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这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
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压缩包 : 5956448vhdl_development_board_sources.rar 列表 VHDL_Development_Board_Sources\综合实验\数字时钟\clock.asm.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock.bdf VHDL_Development_Board_Sources\综合实验\数字时钟\clock.cdf VHDL_Development_Board_Sources\综合实验\数字时钟\clock.done VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.eqn VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock.flow.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.eqn VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock.pin VHDL_Development_Board_Sources\综合实验\数字时钟\clock.pof VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qpf VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qsf VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qws VHDL_Development_Board_Sources\综合实验\数字时钟\clock.tan.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock.tan.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock_assignment_defaults.qdf VHDL_Development_Board_Sources\综合实验\数字时钟\cmp_state.ini VHDL_Development_Board_Sources\综合实验\数字时钟\decode47.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\decode47.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\fen1.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\fen1.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\fen100.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\fen100.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\fen24.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\fen24.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\fen60.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\fen60.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.cmp VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0_wave0.jpg VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0_waveforms.html VHDL_Development_Board_Sources\综合实验\数字时钟\sel.bsf VHDL_Development_Board_Sources\综合实验\数字时钟\sel.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\serv_req_info.txt VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.asm.talkback.xml VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.fit.talkback.xml VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.map.talkback.xml VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.rpp.talkback.xml VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.tan.talkback.xml VHDL_Development_Board_Sources\综合实验\数字时钟\talkback VHDL_Development_Board_Sources\综合实验\数字时钟\db\add_sub_0eh.tdf VHDL_Development_Board_Sources\综合实验\数字时钟\db\add_sub_9ph.tdf VHDL_Development_Board_Sources\综合实验\数字时钟\db\add_sub_aph.tdf VHDL_Development_Board_Sources\综合实验\数字时钟\db\add_sub_bph.tdf VHDL_Development_Board_Sources\综合实验\数字时钟\db\add_sub_vdh.tdf VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(0).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(0).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(1).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(1).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(10).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(10).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(2).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(2).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(3).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(3).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(4).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(4).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(5).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(5).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(6).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(6).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(7).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(7).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(8).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(8).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(9).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock(9).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(0).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(0).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(1).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(1).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(10).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(10).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(11).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(11).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(12).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(12).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(13).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(13).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(14).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(14).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(15).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(15).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(16).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(16).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(17).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(17).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(18).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(18).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(2).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(2).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(3).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(3).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(4).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(4).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(5).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(5).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(6).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(6).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(7).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(7).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(8).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(8).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(9).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.(9).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.asm.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cbx.xml VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cmp.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cmp.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cmp.rdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cmp.tdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.cmp0.ddb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.db_info VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.eco.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.fit.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.frm.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.hif VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.map.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.map.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.map.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.pre_map.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.pre_map.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.psp VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.rpp.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.rtlv.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.rtlv_sg.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.sgate.rvd VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.sgdiff.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.sgdiff.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.sld_design_entry.sci VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.swb.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.syn_hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock.tan.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock_cmp.qrpt VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock_hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\db\clock_syn_hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\db VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.asm.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.done VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.fit.eqn VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.fit.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.fit.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.flow.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.map.eqn VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.map.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.map.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.pin VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.pof VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.qpf VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.qsf VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.qws VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.tan.rpt VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.tan.summary VHDL_Development_Board_Sources\综合实验\数字时钟\clock\clock.vhd VHDL_Development_Board_Sources\综合实验\数字时钟\clock\cmp_state.ini VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(0).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(0).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(1).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(1).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(10).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(10).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(11).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(11).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(2).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(2).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(3).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(3).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(4).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(4).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(5).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(5).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(6).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(6).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(7).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(7).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(8).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(8).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(9).cnf.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.(9).cnf.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.asm.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cbx.xml VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cmp.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cmp.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cmp.rdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cmp.tdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.cmp0.ddb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.db_info VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.eco.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.fit.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.hif VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.map.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.map.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.map.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.pre_map.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.pre_map.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.psp VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.rtlv.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.rtlv_sg.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.sgdiff.cdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.sgdiff.hdb VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.sld_design_entry.sci VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.syn_hier_info VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db\clock.tan.qmsg VHDL_Development_Board_Sources\综合实验\数字时钟\clock\db VHDL_Development_Board_Sources\综合实验\数字时钟\clock VHDL_Development_Board_Sources\综合实验\数字时钟 VHDL_Development_Board_Sources\综合实验\交通灯\traffic\cmp_state.ini VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.asm.rpt VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.done VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.fit.eqn VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.fit.rpt VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.fit.summary VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.flow.rpt VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.map.eqn VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.map.rpt VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.map.summary VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.pin VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.pof VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.qpf VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.qsf VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.qws VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.tan.rpt VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.tan.summary VHDL_Development_Board_Sources\综合实验\交通灯\traffic\traffic.vhd VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(0).cnf.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(0).cnf.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(1).cnf.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(1).cnf.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(2).cnf.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.(2).cnf.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.asm.qmsg VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cbx.xml VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cmp.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cmp.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cmp.rdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cmp.tdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.cmp0.ddb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.db_info VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.eco.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.fit.qmsg VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.hier_info VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.hif VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.map.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.map.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.map.qmsg VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.pre_map.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.pre_map.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.psp VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.rtlv.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.rtlv_sg.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.sgdiff.cdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.sgdiff.hdb VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.sld_design_entry.sci VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.syn_hier_info VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db\traffic.tan.qmsg VHDL_Development_Board_Sources\综合实验\交通灯\traffic\db VHDL_Development_Board_Sources\综合实验\交通灯\traffic VHDL_Development_Board_Sources\综合实验\交通灯 VHDL_Development_Board_Sources\综合实验 VHDL_Development_Board_Sources\接口实验\跑马灯\cmp_state.ini VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.asm.rpt VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.done VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.fit.eqn VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.fit.rpt VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.fit.summary VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.flow.rpt VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.map.eqn VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.map.rpt VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.map.summary VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.pin VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.pof VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.qpf VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.qsf VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.qws VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.tan.rpt VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.tan.summary VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.vhd VHDL_Development_Board_Sources\接口实验\跑马灯\ledwater.vhd.bak VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(0).cnf.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(0).cnf.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(1).cnf.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(1).cnf.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(2).cnf.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.(2).cnf.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.asm.qmsg VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cbx.xml VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cmp.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cmp.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cmp.rdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cmp.tdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.cmp0.ddb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.db_info VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.eco.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.fit.qmsg VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.hier_info VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.hif VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.map.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.map.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.map.qmsg VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.pre_map.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.pre_map.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.psp VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.rtlv.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.rtlv_sg.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.sgdiff.cdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.sgdiff.hdb VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.syn_hier_info VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater.tan.qmsg VHDL_Development_Board_Sources\接口实验\跑马灯\db\ledwater_cmp.qrpt VHDL_Development_Board_Sources\接口实验\跑马灯\db VHDL_Development_Board_Sources\接口实验\跑马灯 VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.asm.rpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.cdf VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.done VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.fit.eqn VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.fit.rpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.fit.summary VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.flow.rpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.map.eqn VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.map.rpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.map.summary VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.pin VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.pof VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.qpf VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.qsf VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.qws VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.tan.rpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.tan.summary VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.vhd VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer.vhd.bak VHDL_Development_Board_Sources\接口实验\蜂鸣器\cmp_state.ini VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\add_sub_7ph.tdf VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(0).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(0).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(1).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(1).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(10).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(10).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(11).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(11).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(2).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(2).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(3).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(3).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(4).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(4).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(5).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(5).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(6).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(6).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(7).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(7).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(8).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(8).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(9).cnf.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.(9).cnf.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.asm.qmsg VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cbx.xml VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cmp.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cmp.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cmp.rdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cmp.tdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.cmp0.ddb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.db_info VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.eco.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.fit.qmsg VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.hier_info VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.hif VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.map.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.map.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.map.qmsg VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.pre_map.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.pre_map.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.psp VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.rtlv.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.rtlv_sg.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.sgdiff.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.sgdiff.hdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.syn_hier_info VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer.tan.qmsg VHDL_Development_Board_Sources\接口实验\蜂鸣器\db\buzzer_cmp.qrpt VHDL_Development_Board_Sources\接口实验\蜂鸣器\db VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\buzzer.qpf VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\buzzer.qsf VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\buzzer.qws VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\buzzer.vhd VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\cmp_state.ini VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\db\buzzer.db_info VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\db\buzzer.eco.cdb VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\db\buzzer.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer\db VHDL_Development_Board_Sources\接口实验\蜂鸣器\buzzer VHDL_Development_Board_Sources\接口实验\蜂鸣器 VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\cmp_state.ini VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.asm.rpt VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.done VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.fit.eqn VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.fit.rpt VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.fit.summary VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.flow.rpt VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.map.eqn VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.map.rpt VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.map.summary VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.pin VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.pof VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.qpf VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.qsf VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.qws VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.tan.rpt VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.tan.summary VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\key0.vhd VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.(0).cnf.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.(0).cnf.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.(1).cnf.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.(1).cnf.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.asm.qmsg VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cbx.xml VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cmp.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cmp.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cmp.rdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cmp.tdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.cmp0.ddb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.db_info VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.eco.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.fit.qmsg VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.hier_info VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.hif VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.map.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.map.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.map.qmsg VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.pre_map.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.pre_map.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.psp VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.rtlv.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.rtlv_sg.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.sgdiff.cdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.sgdiff.hdb VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.syn_hier_info VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db\key0.tan.qmsg VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0\db VHDL_Development_Board_Sources\接口实验\矩阵键盘\key0 VHDL_Development_Board_Sources\接口实验\矩阵键盘 VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\cjdk.qpf VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\cjdk.qsf VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\cjdk.qws VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\cmp_state.ini VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.asm.rpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.done VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.fit.eqn VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.fit.rpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.fit.summary VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.flow.rpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.map.eqn VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.map.rpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.map.summary VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.pin VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.pof VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.qpf VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.qsf VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.qws VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.tan.rpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.tan.summary VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\dial2.vhd VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\serv_req_info.txt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\undo_redo.txt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\cjdk.db_info VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\cjdk.eco.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\cjdk.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.(0).cnf.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.(0).cnf.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.(1).cnf.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.(1).cnf.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.asm.qmsg VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.atom.rvd VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cbx.xml VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cmp.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cmp.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cmp.rdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cmp.tdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.cmp0.ddb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.db_info VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.eco.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.fit.qmsg VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.hier_info VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.hif VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.map.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.map.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.map.qmsg VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.pre_map.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.pre_map.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.psp VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.rpp.qmsg VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.rtlv.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.rtlv_sg.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.sgate.rvd VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.sgdiff.cdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.sgdiff.hdb VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.syn_hier_info VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2.tan.qmsg VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db\dial2_cmp.qrpt VHDL_Development_Board_Sources\接口实验\拨码开关\dial2\db VHDL_Development_Board_Sources\接口实验\拨码开关\dial2 VHDL_Development_Board_Sources\接口实验\拨码开关 VHDL_Development_Board_Sources\接口实验\串口\cmp_state.ini VHDL_Development_Board_Sources\接口实验\串口\serial.asm.rpt VHDL_Development_Board_Sources\接口实验\串口\serial.cdf VHDL_Development_Board_Sources\接口实验\串口\serial.done VHDL_Development_Board_Sources\接口实验\串口\serial.fit.eqn VHDL_Development_Board_Sources\接口实验\串口\serial.fit.rpt VHDL_Development_Board_Sources\接口实验\串口\serial.fit.summary VHDL_Development_Board_Sources\接口实验\串口\serial.flow.rpt VHDL_Development_Board_Sources\接口实验\串口\serial.map.eqn VHDL_Development_Board_Sources\接口实验\串口\serial.map.rpt VHDL_Development_Board_Sources\接口实验\串口\serial.map.summary VHDL_Development_Board_Sources\接口实验\串口\serial.pin VHDL_Development_Board_Sources\接口实验\串口\serial.pof VHDL_Development_Board_Sources\接口实验\串口\serial.qpf VHDL_Development_Board_Sources\接口实验\串口\serial.qsf VHDL_Development_Board_Sources\接口实验\串口\serial.qws VHDL_Development_Board_Sources\接口实验\串口\serial.tan.rpt VHDL_Development_Board_Sources\接口实验\串口\serial.tan.summary VHDL_Development_Board_Sources\接口实验\串口\serial.vhd VHDL_Development_Board_Sources\接口实验\串口\serial.vhd.bak VHDL_Development_Board_Sources\接口实验\串口\transcript VHDL_Development_Board_Sources\接口实验\串口\db\add_sub_5ph.tdf VHDL_Development_Board_Sources\接口实验\串口\db\add_sub_aph.tdf VHDL_Development_Board_Sources\接口实验\串口\db\serial.(0).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(0).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(1).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(1).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(10).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(10).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(11).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(11).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(12).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(12).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(2).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(2).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(3).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(3).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(4).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(4).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(5).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(5).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(6).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(6).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(7).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(7).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(8).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(8).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(9).cnf.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.(9).cnf.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.asm.qmsg VHDL_Development_Board_Sources\接口实验\串口\db\serial.cbx.xml VHDL_Development_Board_Sources\接口实验\串口\db\serial.cmp.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.cmp.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.cmp.rdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.cmp.tdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.cmp0.ddb VHDL_Development_Board_Sources\接口实验\串口\db\serial.db_info VHDL_Development_Board_Sources\接口实验\串口\db\serial.eco.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.fit.qmsg VHDL_Development_Board_Sources\接口实验\串口\db\serial.hier_info VHDL_Development_Board_Sources\接口实验\串口\db\serial.hif VHDL_Development_Board_Sources\接口实验\串口\db\serial.map.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.map.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.map.qmsg VHDL_Development_Board_Sources\接口实验\串口\db\serial.pre_map.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.pre_map.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.psp VHDL_Development_Board_Sources\接口实验\串口\db\serial.rtlv.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.rtlv_sg.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.rtlv_sg_swap.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.sgdiff.cdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.sgdiff.hdb VHDL_Development_Board_Sources\接口实验\串口\db\serial.sld_design_entry.sci VHDL_Development_Board_Sources\接口实验\串口\db\serial.sld_design_entry_dsc.sci VHDL_Development_Board_Sources\接口实验\串口\db\serial.syn_hier_info VHDL_Development_Board_Sources\接口实验\串口\db\serial.tan.qmsg VHDL_Development_Board_Sources\接口实验\串口\db\serial_cmp.qrpt VHDL_Development_Board_Sources\接口实验\串口\db VHDL_Development_Board_Sources\接口实验\串口 VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\atcl_error.txt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\char_ram.vhd VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\clklogic.gdf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\cmp_state.ini VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.asm.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.done VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.fit.eqn VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.fit.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.fit.summary VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.flow.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.map.eqn VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.map.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.map.summary VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.pin VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.pof VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.qpf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.qsf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.qws VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.sim.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.tan.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.tan.summary VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.vhd VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd.vwf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd_assignment_defaults.qdf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\程序说明.doc VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\.untf VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\automake.log VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.bld VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.cel VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.cmd_log VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.dhp VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.gyd VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.imp VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.jed VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.lso VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.mfd VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.ngc VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.ngd VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.ngr VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.npl VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.pnx VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.prj VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.rpt VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.syr VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.tim VHDL_Development_Board_Sources\接口实验\lcd液晶显示\lcd\lcd\lcd.ucf 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