文件名称:canbus(FPGA)
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基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
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压缩包 : 75448152canbus(fpga).rar 列表 canbus canbus\.untf canbus\__projnav.log canbus\automake.log canbus\can_acf.v canbus\can_bsp.v canbus\can_btl.v canbus\can_crc.v canbus\can_defines.v canbus\can_fifo.cmd_log canbus\can_fifo.lso canbus\can_fifo.ngc canbus\can_fifo.ngr canbus\can_fifo.prj canbus\can_fifo.stx canbus\can_fifo.syr canbus\can_fifo.v canbus\can_fifo_vhdl.prj canbus\can_ibo.v canbus\can_register.v canbus\can_register_asyn.v canbus\can_register_asyn_syn.cmd_log canbus\can_register_asyn_syn.lso canbus\can_register_asyn_syn.ngc canbus\can_register_asyn_syn.ngr canbus\can_register_asyn_syn.prj canbus\can_register_asyn_syn.stx canbus\can_register_asyn_syn.syr canbus\can_register_asyn_syn.v canbus\can_register_asyn_syn_vhdl.prj canbus\can_register_syn.v canbus\can_registers.lso canbus\can_registers.prj canbus\can_registers.stx canbus\can_registers.v canbus\can_registers_vhdl.prj canbus\can_testbench.fdo canbus\can_testbench.ndo canbus\can_testbench.udo canbus\can_testbench.v canbus\can_testbench_defines.v canbus\can_top.bld canbus\can_top.cmd_log canbus\can_top.ldo canbus\can_top.lso canbus\can_top.ngc canbus\can_top.ngd canbus\can_top.ngr canbus\can_top.prj canbus\can_top.stx canbus\can_top.syr canbus\can_top.v canbus\can_top.vhdsim_xlate canbus\can_top.xlate_nlf canbus\can_top_translate.nlf canbus\can_top_translate.vhd canbus\can_top_vhdl.prj canbus\canbus.dhp canbus\canbus.npl canbus\coregen.log canbus\coregen.prj canbus\prjname.lso canbus\timescale.v canbus\transcript canbus\xst canbus\xst\work canbus\xst\work\hdllib.ref canbus\xst\work\vlg70 canbus\xst\work\vlg70\can_top.bin canbus\xst\work\vlg5E canbus\xst\work\vlg5E\can_register.bin canbus\xst\work\vlg4F canbus\xst\work\vlg4F\can_acf.bin canbus\xst\work\vlg49 canbus\xst\work\vlg49\can_crc.bin canbus\xst\work\vlg49\can_registers.bin canbus\xst\work\vlg48 canbus\xst\work\vlg48\can_register_asyn.bin canbus\xst\work\vlg43 canbus\xst\work\vlg43\can_btl.bin canbus\xst\work\vlg42 canbus\xst\work\vlg42\can_bsp.bin canbus\xst\work\vlg31 canbus\xst\work\vlg31\can_register_asyn_syn.bin canbus\xst\work\vlg1B canbus\xst\work\vlg1B\can_ibo.bin canbus\xst\work\vlg01 canbus\xst\work\vlg01\can_fifo.bin canbus\work canbus\work\_info canbus\work\glbl canbus\work\glbl\_primary.dat canbus\work\glbl\_primary.vhd canbus\work\glbl\verilog.asm canbus\work\can_top canbus\work\can_top\_primary.dat canbus\work\can_top\_primary.vhd canbus\work\can_top\verilog.asm canbus\work\can_testbench canbus\work\can_testbench\_primary.dat canbus\work\can_testbench\_primary.vhd canbus\work\can_testbench\verilog.asm canbus\work\can_registers canbus\work\can_registers\_primary.dat canbus\work\can_registers\_primary.vhd canbus\work\can_registers\verilog.asm canbus\work\can_register_asyn_syn canbus\work\can_register_asyn_syn\_primary.dat canbus\work\can_register_asyn_syn\_primary.vhd canbus\work\can_register_asyn_syn\verilog.asm canbus\work\can_register_asyn canbus\work\can_register_asyn\_primary.dat canbus\work\can_register_asyn\_primary.vhd canbus\work\can_register_asyn\verilog.asm canbus\work\can_register canbus\work\can_register\_primary.dat canbus\work\can_register\_primary.vhd canbus\work\can_register\verilog.asm canbus\work\can_ibo canbus\work\can_ibo\_primary.dat canbus\work\can_ibo\_primary.vhd canbus\work\can_ibo\verilog.asm canbus\work\can_fifo canbus\work\can_fifo\_primary.dat canbus\work\can_fifo\_primary.vhd canbus\work\can_fifo\verilog.asm canbus\work\can_crc canbus\work\can_crc\_primary.dat canbus\work\can_crc\_primary.vhd canbus\work\can_crc\verilog.asm canbus\work\can_btl canbus\work\can_btl\_primary.dat canbus\work\can_btl\_primary.vhd canbus\work\can_btl\verilog.asm canbus\work\can_bsp canbus\work\can_bsp\_primary.dat canbus\work\can_bsp\_primary.vhd canbus\work\can_bsp\verilog.asm canbus\work\can_acf canbus\work\can_acf\_primary.dat canbus\work\can_acf\_primary.vhd canbus\work\can_acf\verilog.asm canbus\_ngo canbus\_ngo\netlist.lst canbus\__projnav canbus\__projnav\can_fifo.xst canbus\__projnav\can_register_asyn_syn.xst canbus\__projnav\can_registers.xst canbus\__projnav\can_top.xst canbus\__projnav\canbus.gfl canbus\__projnav\canbus_flowplus.gfl canbus\__projnav\coregen.rsp canbus\__projnav\ednTOngd_tcl.rsp canbus\__projnav\runXst_tcl.rsp canbus\__projnav\xst_sprjTOstx_tcl.rsp