文件名称:Quaalu
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ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲-ALU arithmetic logic unit to achieve a simple, using VHDL language, can be additive, subtractive, and the place and move around only one clock pulse
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压缩包 : 9927403quaalu.rar 列表 alu\ceshi.fit.rpt alu\ceshi.fit.summary alu\ceshi.flow.rpt alu\ceshi.map.eqn alu\ceshi.map.rpt alu\ceshi.map.summary alu\ceshi.qpf alu\ceshi.qsf alu\ceshi.qws alu\ceshi.vhd alu\cmp_state.ini alu\db\add_sub_djh.tdf alu\db\ceshi.(0).cnf.cdb alu\db\ceshi.(0).cnf.hdb alu\db\ceshi.(1).cnf.cdb alu\db\ceshi.(1).cnf.hdb alu\db\ceshi.(2).cnf.cdb alu\db\ceshi.(2).cnf.hdb alu\db\ceshi.(3).cnf.cdb alu\db\ceshi.(3).cnf.hdb alu\db\ceshi.(4).cnf.cdb alu\db\ceshi.(4).cnf.hdb alu\db\ceshi.(5).cnf.cdb alu\db\ceshi.(5).cnf.hdb alu\db\ceshi.(6).cnf.cdb alu\db\ceshi.(6).cnf.hdb alu\db\ceshi.(7).cnf.cdb alu\db\ceshi.(7).cnf.hdb alu\db\ceshi.(8).cnf.cdb alu\db\ceshi.(8).cnf.hdb alu\db\ceshi.(9).cnf.cdb alu\db\ceshi.(9).cnf.hdb alu\db\ceshi.cbx.xml alu\db\ceshi.cmp.cdb alu\db\ceshi.cmp.hdb alu\db\ceshi.cmp.rdb alu\db\ceshi.db_info alu\db\ceshi.eco.cdb alu\db\ceshi.fit.qmsg alu\db\ceshi.hier_info alu\db\ceshi.hif alu\db\ceshi.map.cdb alu\db\ceshi.map.hdb alu\db\ceshi.map.qmsg alu\db\ceshi.pre_map.cdb alu\db\ceshi.pre_map.hdb alu\db\ceshi.psp alu\db\ceshi.rtlv.hdb alu\db\ceshi.rtlv_sg.cdb alu\db\ceshi.rtlv_sg_swap.cdb alu\db\ceshi.sgdiff.cdb alu\db\ceshi.sgdiff.hdb alu\db\ceshi.sld_design_entry.sci alu\db\ceshi.sld_design_entry_dsc.sci alu\db\ceshi.syn_hier_info alu\db\ceshi_cmp.qrpt alu\db alu