文件名称:vhdl-2
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UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
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压缩包 : 25811242vhdl-2.rar 列表 VHDL源代码 VHDL源代码\vhdl_example.html VHDL源代码\adder_nbit_generate.txt VHDL源代码\adder_variety_style.txt VHDL源代码\address_decoder_m68008.txt VHDL源代码\chess_clock.txt VHDL源代码\comparator8.txt VHDL源代码\comparetor_magnitude.txt VHDL源代码\compinst.vhd VHDL源代码\condsig.vhd VHDL源代码\condsigm.vhd VHDL源代码\conversion_altera.vhd VHDL源代码\counter_conversion.txt VHDL源代码\counter_generate.txt VHDL源代码\counter_mod16_jk.txt VHDL源代码\counter_nbit.txt VHDL源代码\counter_pload.txt VHDL源代码\counter_wait.txt VHDL源代码\counters_altera.vhd VHDL源代码\cpu_3rd_package.txt VHDL源代码\cpu_core.txt VHDL源代码\CPU_ram.txt VHDL源代码\CPU_rom.txt VHDL源代码\CPU_system.txt VHDL源代码\dc_motor.vhd VHDL源代码\decoder_bcd_to_7segment.txt VHDL源代码\decoder_hct139.txt VHDL源代码\d-filp-flop_hct175.txt VHDL源代码\fifo.txt VHDL源代码\hamming_decoder.txt VHDL源代码\hamming_encoder.txt VHDL源代码\hct245.txt VHDL源代码\latchinf.vhd VHDL源代码\majority_voter.txt VHDL源代码\mancala.vhd VHDL源代码\mealy1.txt VHDL源代码\moor1.txt VHDL源代码\moor2.txt VHDL源代码\multiplexer_ifelse.txt VHDL源代码\multiplier_booth.txt VHDL源代码\pelian_contrller.txt VHDL源代码\priority_encoder_highest.txt VHDL源代码\priority_encoder_ls.vhd VHDL源代码\pseudorandom.vhd VHDL源代码\ram_16x8.txt VHDL源代码\ram_LS.vhd VHDL源代码\random_generator.txt VHDL源代码\reg12.vhd VHDL源代码\reginf.vhd VHDL源代码\register_374.txt VHDL源代码\selsigen.vhd VHDL源代码\shift_register_164.txt VHDL源代码\smart_waveform.vhd VHDL源代码\State_areset.txt VHDL源代码\state_classic.txt VHDL源代码\state_moor_mealy.txt VHDL源代码\state_variable.txt VHDL源代码\statmach_altera.vhd VHDL源代码\step_motor.vhd VHDL源代码\testadder.vhd VHDL源代码\traffic_ls.vhd VHDL源代码\uart_ls.vhd VHDL源代码\universal_register.txt VHDL源代码\adder.vhd