文件名称:Xilinx_4
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Xilinx ISE官方源代码盘
第六章-Xilinx ISE official source was the sixth chapter
第六章-Xilinx ISE official source was the sixth chapter
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压缩包 : 77433656xilinx_4.rar 列表 Xilinx_4 Xilinx_4\Example-6-1 Xilinx_4\Example-6-1\6_1pro Xilinx_4\Example-6-1\6_1pro\_ngo Xilinx_4\Example-6-1\Source Xilinx_4\Example-6-2 Xilinx_4\Example-6-2\6-2 Xilinx_4\Example-6-2\6-2\add_2bit Xilinx_4\Example-6-2\6-2\source Xilinx_4\Example-6-2\Source Xilinx_4\Example-6-1\6_1pro\6_1pro.jid Xilinx_4\Example-6-1\6_1pro\6_1pro.npl Xilinx_4\Example-6-1\6_1pro\6_1pro.ptf Xilinx_4\Example-6-1\6_1pro\automake.log Xilinx_4\Example-6-1\6_1pro\chkdata.err Xilinx_4\Example-6-1\6_1pro\ddrfd.jhd Xilinx_4\Example-6-1\6_1pro\load_gen.jhd Xilinx_4\Example-6-1\6_1pro\m2_1.jhd Xilinx_4\Example-6-1\6_1pro\par.opt Xilinx_4\Example-6-1\6_1pro\piso.jhd Xilinx_4\Example-6-1\6_1pro\tx2bit.bld Xilinx_4\Example-6-1\6_1pro\tx2bit.cel Xilinx_4\Example-6-1\6_1pro\tx2bit.dly Xilinx_4\Example-6-1\6_1pro\tx2bit.fnf Xilinx_4\Example-6-1\6_1pro\tx2bit.jhd Xilinx_4\Example-6-1\6_1pro\tx2bit.mrp Xilinx_4\Example-6-1\6_1pro\tx2bit.nc1 Xilinx_4\Example-6-1\6_1pro\tx2bit.ncd Xilinx_4\Example-6-1\6_1pro\tx2bit.ngc Xilinx_4\Example-6-1\6_1pro\tx2bit.ngd Xilinx_4\Example-6-1\6_1pro\tx2bit.ngm Xilinx_4\Example-6-1\6_1pro\tx2bit.pad Xilinx_4\Example-6-1\6_1pro\tx2bit.par Xilinx_4\Example-6-1\6_1pro\tx2bit.pcf Xilinx_4\Example-6-1\6_1pro\tx2bit.prj Xilinx_4\Example-6-1\6_1pro\tx2bit.sdc Xilinx_4\Example-6-1\6_1pro\tx2bit.syr Xilinx_4\Example-6-1\6_1pro\tx2bit.tlg Xilinx_4\Example-6-1\6_1pro\tx2bit.twr Xilinx_4\Example-6-1\6_1pro\tx2bit.twx Xilinx_4\Example-6-1\6_1pro\tx2bit.ucf Xilinx_4\Example-6-1\6_1pro\tx2bit.ucf.bak Xilinx_4\Example-6-1\6_1pro\tx2bit.xpi Xilinx_4\Example-6-1\6_1pro\tx2bit.xst Xilinx_4\Example-6-1\6_1pro\tx2bit._prj Xilinx_4\Example-6-1\6_1pro\tx2bit_compile.tcl Xilinx_4\Example-6-1\6_1pro\tx2bit_fpga_editor.out Xilinx_4\Example-6-1\6_1pro\tx2bit_fpga_editor_021214_121857.log Xilinx_4\Example-6-1\6_1pro\tx2bit_fpga_editor_021215_160731.log Xilinx_4\Example-6-1\6_1pro\tx2bit_last_ngd.ngd Xilinx_4\Example-6-1\6_1pro\tx2bit_last_ngd_report.bld Xilinx_4\Example-6-1\6_1pro\tx2bit_last_par.ncd Xilinx_4\Example-6-1\6_1pro\tx2bit_map.mfp Xilinx_4\Example-6-1\6_1pro\tx2bit_map.ncd Xilinx_4\Example-6-1\6_1pro\tx2bit_map_fpga_editor_021214_112102.log Xilinx_4\Example-6-1\6_1pro\tx2bit_ngdbuild.nav Xilinx_4\Example-6-1\6_1pro\_editucf.err Xilinx_4\Example-6-1\6_1pro\_editucf.rsp Xilinx_4\Example-6-1\6_1pro\_editucf_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\_map.log Xilinx_4\Example-6-1\6_1pro\_map.rsp Xilinx_4\Example-6-1\6_1pro\_nc1TOncd_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\_ncdTOtwr_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\_ngdTOnc1_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\_ngo\netlist.lst Xilinx_4\Example-6-1\6_1pro\_par.log Xilinx_4\Example-6-1\6_1pro\_par.rsp Xilinx_4\Example-6-1\6_1pro\_prepar.rsp Xilinx_4\Example-6-1\6_1pro\__constEditor_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\__ednTOngd_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\__filesAllClean.fac Xilinx_4\Example-6-1\6_1pro\__launchSyn.tcl Xilinx_4\Example-6-1\6_1pro\__launchTA.tcl Xilinx_4\Example-6-1\6_1pro\__mapFloorPlanner.rsp Xilinx_4\Example-6-1\6_1pro\__mapFloorPlannerAppExewrap.rsp Xilinx_4\Example-6-1\6_1pro\__ngdbuild.rsp Xilinx_4\Example-6-1\6_1pro\__parFloorPlanner.rsp Xilinx_4\Example-6-1\6_1pro\__parFloorPlannerAppExewrap.rsp Xilinx_4\Example-6-1\6_1pro\__posttrc.log Xilinx_4\Example-6-1\6_1pro\__posttrc.rsp Xilinx_4\Example-6-1\6_1pro\__projnav.log Xilinx_4\Example-6-1\6_1pro\__tx2bit_2prj_exewrap.rsp Xilinx_4\Example-6-1\6_1pro\__tx2bit_mapFloorPlanner.err Xilinx_4\Example-6-1\6_1pro\__tx2bit_parFloorPlanner.err Xilinx_4\Example-6-1\Source\ddrfd.v Xilinx_4\Example-6-1\Source\ddrfd.v.bak Xilinx_4\Example-6-1\Source\load_gen.v Xilinx_4\Example-6-1\Source\m2_1.v Xilinx_4\Example-6-1\Source\m2_1.v.bak Xilinx_4\Example-6-1\Source\piso.v Xilinx_4\Example-6-1\Source\tx2bit.cel Xilinx_4\Example-6-1\Source\tx2bit.ucf Xilinx_4\Example-6-1\Source\tx2bit.v Xilinx_4\Example-6-1\示例说明.doc Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit.nmc Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit_fpga_editor_021229_113223.log Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit_fpga_editor_021229_114414.log Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit_fpga_editor_021229_114415.log Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit_fpga_editor_021229_115241.log Xilinx_4\Example-6-2\6-2\add_2bit\add_2bit_fpga_editor_021229_115249.log Xilinx_4\Example-6-2\6-2\source\add_2bit_modult.v Xilinx_4\Example-6-2\Source\add_2bit.nmc Xilinx_4\Example-6-2\Source\add_2bit_fpga_editor_030204_132925.log Xilinx_4\Example-6-2\Source\test_add2_macro.v Xilinx_4\Example-6-2\示例说明.doc