文件名称:Xilinx_2
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Xilinx Ise
官方源代码盘 第四章-Xilinx Ise official source code-Chapter IV
官方源代码盘 第四章-Xilinx Ise official source code-Chapter IV
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压缩包 : 93317469xilinx_2.rar 列表 Xilinx_2 Xilinx_2\Example-4-1 Xilinx_2\Example-4-1\Synplify_Pro Xilinx_2\Example-4-1\Synplify_Pro\Mix Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_4k Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_virtex Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_virtex2 Xilinx_2\Example-4-1\Synplify_Pro\rev_1 Xilinx_2\Example-4-1\Synplify_Pro\rev_1\syntmp Xilinx_2\Example-4-1\Synplify_Pro\rev_2 Xilinx_2\Example-4-1\Synplify_Pro\rev_2\syntmp Xilinx_2\Example-4-1\Synplify_Pro\verilog Xilinx_2\Example-4-1\Synplify_Pro\vhdl Xilinx_2\Example-4-1\Synplify_Pro\源代码 Xilinx_2\Example-4-1\Synplify_Pro\源代码\verilog Xilinx_2\Example-4-1\Synplify_Pro\源代码\VHDL Xilinx_2\Example-4-1\Xilinx示例 Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703 Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\bufgce_instanciate Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\bufgmux_instanciate Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate\frequency_synthesis Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate\phase_shifting Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr\input Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr_instanciate Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr_instanciate\bi_dir_instanciate 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Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\mult_and Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\ram Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\ram\default Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\ram\v2bram_no_change Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\ram\v2bram_read_first Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\ram\v2bram_write_first Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\rom Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\rom\default Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\rom\v2bram Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\sop_instanciate Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\srl_dynamic Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\vhdl\srl_static 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