文件名称:10GE Ethernet
- 所属分类:
- VHDL编程
- 资源属性:
- [C/C++] [源码]
- 上传时间:
- 2020-09-08
- 文件大小:
- 595.92kb
- 下载次数:
- 0次
- 提 供 者:
- 104758548@qq.com
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
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下载文件列表
压缩包 : ethernet_10ge_mac_SV_tb-master.zip 列表 ethernet_10ge_mac_SV_tb-master/ ethernet_10ge_mac_SV_tb-master/.gitignore ethernet_10ge_mac_SV_tb-master/README ethernet_10ge_mac_SV_tb-master/doc/ ethernet_10ge_mac_SV_tb-master/doc/10GB_MAC_CORE_Verification_Plan.pdf ethernet_10ge_mac_SV_tb-master/rtl/ ethernet_10ge_mac_SV_tb-master/rtl/auto_verilog.sh ethernet_10ge_mac_SV_tb-master/rtl/include/ ethernet_10ge_mac_SV_tb-master/rtl/include/CRC32_D64.v ethernet_10ge_mac_SV_tb-master/rtl/include/CRC32_D8.v ethernet_10ge_mac_SV_tb-master/rtl/include/defines.v ethernet_10ge_mac_SV_tb-master/rtl/include/timescale.v ethernet_10ge_mac_SV_tb-master/rtl/include/utils.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/ ethernet_10ge_mac_SV_tb-master/rtl/verilog/fault_sm.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/generic_fifo.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/generic_fifo_ctrl.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/generic_mem_medium.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/generic_mem_small.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/meta_sync.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/meta_sync_single.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/rx_data_fifo.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/rx_dequeue.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/rx_enqueue.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/rx_hold_fifo.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/sync_clk_core.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/sync_clk_wb.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/sync_clk_xgmii_tx.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/tx_data_fifo.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/tx_dequeue.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/tx_enqueue.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/tx_hold_fifo.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/wishbone_if.v ethernet_10ge_mac_SV_tb-master/rtl/verilog/xge_mac.v ethernet_10ge_mac_SV_tb-master/scripts/ ethernet_10ge_mac_SV_tb-master/scripts/Makefile ethernet_10ge_mac_SV_tb-master/scripts/gen_summary.pl ethernet_10ge_mac_SV_tb-master/sim/ ethernet_10ge_mac_SV_tb-master/sim/CLEAN ethernet_10ge_mac_SV_tb-master/sim/runsim ethernet_10ge_mac_SV_tb-master/sim/runsim.coverage ethernet_10ge_mac_SV_tb-master/sim/runsim.verilog_tb ethernet_10ge_mac_SV_tb-master/testbench/ ethernet_10ge_mac_SV_tb-master/testbench/coverage.sv ethernet_10ge_mac_SV_tb-master/testbench/driver.sv ethernet_10ge_mac_SV_tb-master/testbench/env.sv ethernet_10ge_mac_SV_tb-master/testbench/monitor.sv ethernet_10ge_mac_SV_tb-master/testbench/packet.sv ethernet_10ge_mac_SV_tb-master/testbench/scoreboard.sv ethernet_10ge_mac_SV_tb-master/testbench/testbench.sv ethernet_10ge_mac_SV_tb-master/testbench/verilog/ ethernet_10ge_mac_SV_tb-master/testbench/verilog/packets_tx.txt ethernet_10ge_mac_SV_tb-master/testbench/verilog/tb_xge_mac.sv ethernet_10ge_mac_SV_tb-master/testbench/xge_mac_interface.sv ethernet_10ge_mac_SV_tb-master/testcases/ ethernet_10ge_mac_SV_tb-master/testcases/bringup_loopback/ ethernet_10ge_mac_SV_tb-master/testcases/bringup_loopback/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/bringup_loopback/runsim ethernet_10ge_mac_SV_tb-master/testcases/bringup_loopback/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/missing_eop/ ethernet_10ge_mac_SV_tb-master/testcases/missing_eop/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/missing_eop/runsim ethernet_10ge_mac_SV_tb-master/testcases/missing_eop/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/missing_sop/ ethernet_10ge_mac_SV_tb-master/testcases/missing_sop/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/missing_sop/runsim ethernet_10ge_mac_SV_tb-master/testcases/missing_sop/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/original_testcase/ ethernet_10ge_mac_SV_tb-master/testcases/original_testcase/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/original_testcase/runsim.verilog_tb ethernet_10ge_mac_SV_tb-master/testcases/original_testcase/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/oversize_packet/ ethernet_10ge_mac_SV_tb-master/testcases/oversize_packet/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/oversize_packet/runsim ethernet_10ge_mac_SV_tb-master/testcases/oversize_packet/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/undersize_packet/ ethernet_10ge_mac_SV_tb-master/testcases/undersize_packet/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/undersize_packet/runsim ethernet_10ge_mac_SV_tb-master/testcases/undersize_packet/testcase.sv ethernet_10ge_mac_SV_tb-master/testcases/zero_ipg_packet/ ethernet_10ge_mac_SV_tb-master/testcases/zero_ipg_packet/CLEAN ethernet_10ge_mac_SV_tb-master/testcases/zero_ipg_packet/runsim ethernet_10ge_mac_SV_tb-master/testcases/zero_ipg_packet/testcase.sv
压缩包 : ethmac10g-master.zip 列表 ethmac10g-master/ ethmac10g-master/bench/ ethmac10g-master/bench/Receive_tb.v ethmac10g-master/bench/TransmitTop.mpf ethmac10g-master/bench/TransmitTop_CRC_tb.v ethmac10g-master/bench/TransmitTop_min_frame_tb.v ethmac10g-master/bench/TransmitTop_pause_tb.v ethmac10g-master/bench/TransmitTop_tb.v ethmac10g-master/bench/debug.do ethmac10g-master/bench/debug_large.do ethmac10g-master/bench/debug_pause.do ethmac10g-master/bench/management_tb.v ethmac10g-master/doc/ ethmac10g-master/doc/Receive.pdf ethmac10g-master/doc/management.pdf ethmac10g-master/doc/transmit.pdf ethmac10g-master/rtl/ ethmac10g-master/rtl/verilog/ ethmac10g-master/rtl/verilog/mgmt/ ethmac10g-master/rtl/verilog/mgmt/manage_registers.v ethmac10g-master/rtl/verilog/mgmt/management_top.v ethmac10g-master/rtl/verilog/mgmt/mdio.v ethmac10g-master/rtl/verilog/rx_engine/ ethmac10g-master/rtl/verilog/rx_engine/CRC32_D64.v ethmac10g-master/rtl/verilog/rx_engine/CRC32_D8.v ethmac10g-master/rtl/verilog/rx_engine/SwitchAsyncFIFO.v ethmac10g-master/rtl/verilog/rx_engine/SwitchSyncFIFO.v ethmac10g-master/rtl/verilog/rx_engine/counter.v ethmac10g-master/rtl/verilog/rx_engine/rxCRC.v ethmac10g-master/rtl/verilog/rx_engine/rxClkgen.v ethmac10g-master/rtl/verilog/rx_engine/rxDAchecker.v ethmac10g-master/rtl/verilog/rx_engine/rxDataPath.v ethmac10g-master/rtl/verilog/rx_engine/rxLenTypChecker.v ethmac10g-master/rtl/verilog/rx_engine/rxLinkFaultState.v ethmac10g-master/rtl/verilog/rx_engine/rxNumCounter.v ethmac10g-master/rtl/verilog/rx_engine/rxRSIO.v ethmac10g-master/rtl/verilog/rx_engine/rxRSLayer.v ethmac10g-master/rtl/verilog/rx_engine/rxReceiveEngine.ucf ethmac10g-master/rtl/verilog/rx_engine/rxReceiveEngine.v ethmac10g-master/rtl/verilog/rx_engine/rxStatModule.v ethmac10g-master/rtl/verilog/rx_engine/rxStateMachine.v ethmac10g-master/rtl/verilog/rx_engine/timescale.v ethmac10g-master/rtl/verilog/rx_engine/xgiga_define.v ethmac10g-master/rtl/verilog/tx_engine/ ethmac10g-master/rtl/verilog/tx_engine/CRC32_D64.v ethmac10g-master/rtl/verilog/tx_engine/CRC32_D8.v ethmac10g-master/rtl/verilog/tx_engine/TransmitTop.v ethmac10g-master/rtl/verilog/tx_engine/ack_counter.v ethmac10g-master/rtl/verilog/tx_engine/byte_counter.v
压缩包 : xge_mac-master.zip 列表 xge_mac-master/ xge_mac-master/README.TXT xge_mac-master/doc/ xge_mac-master/doc/drawings.odg xge_mac-master/doc/xge_mac_spec.odt xge_mac-master/doc/xge_mac_spec.pdf xge_mac-master/rtl/ xge_mac-master/rtl/auto_verilog.sh xge_mac-master/rtl/custom.el xge_mac-master/rtl/include/ xge_mac-master/rtl/include/CRC32_D64.v xge_mac-master/rtl/include/CRC32_D8.v xge_mac-master/rtl/include/defines.v xge_mac-master/rtl/include/timescale.v xge_mac-master/rtl/include/utils.v xge_mac-master/rtl/verilog/ xge_mac-master/rtl/verilog/fault_sm.v xge_mac-master/rtl/verilog/generic_fifo.v xge_mac-master/rtl/verilog/generic_fifo_ctrl.v xge_mac-master/rtl/verilog/generic_mem_medium.v xge_mac-master/rtl/verilog/generic_mem_small.v xge_mac-master/rtl/verilog/meta_sync.v xge_mac-master/rtl/verilog/meta_sync_single.v xge_mac-master/rtl/verilog/rx_data_fifo.v xge_mac-master/rtl/verilog/rx_dequeue.v xge_mac-master/rtl/verilog/rx_enqueue.v xge_mac-master/rtl/verilog/rx_hold_fifo.v xge_mac-master/rtl/verilog/sync_clk_core.v xge_mac-master/rtl/verilog/sync_clk_wb.v xge_mac-master/rtl/verilog/sync_clk_xgmii_tx.v xge_mac-master/rtl/verilog/tx_data_fifo.v xge_mac-master/rtl/verilog/tx_dequeue.v xge_mac-master/rtl/verilog/tx_enqueue.v xge_mac-master/rtl/verilog/tx_hold_fifo.v xge_mac-master/rtl/verilog/wishbone_if.v xge_mac-master/rtl/verilog/xge_mac.v xge_mac-master/sim/ xge_mac-master/sim/systemc/ xge_mac-master/sim/systemc/compile.sh xge_mac-master/sim/systemc/run.sh xge_mac-master/sim/systemc/sc.mk xge_mac-master/sim/systemc/verilator.cmd xge_mac-master/sim/verilog/ xge_mac-master/sim/verilog/sim.do xge_mac-master/tbench/ xge_mac-master/tbench/systemc/ xge_mac-master/tbench/systemc/crc.cpp xge_mac-master/tbench/systemc/crc.h xge_mac-master/tbench/systemc/sc_cpu_if.cpp xge_mac-master/tbench/systemc/sc_cpu_if.h xge_mac-master/tbench/systemc/sc_main.cpp xge_mac-master/tbench/systemc/sc_packet.cpp xge_mac-master/tbench/systemc/sc_packet.h xge_mac-master/tbench/systemc/sc_pkt_generator.cpp xge_mac-master/tbench/systemc/sc_pkt_generator.h xge_mac-master/tbench/systemc/sc_pkt_if.cpp xge_mac-master/tbench/systemc/sc_pkt_if.h xge_mac-master/tbench/systemc/sc_scoreboard.cpp xge_mac-master/tbench/systemc/sc_scoreboard.h xge_mac-master/tbench/systemc/sc_testbench.cpp xge_mac-master/tbench/systemc/sc_testbench.h xge_mac-master/tbench/systemc/sc_testcases.cpp xge_mac-master/tbench/systemc/sc_testcases.h xge_mac-master/tbench/systemc/sc_xgmii_if.cpp xge_mac-master/tbench/systemc/sc_xgmii_if.h xge_mac-master/tbench/verilog/ xge_mac-master/tbench/verilog/packets_tx.txt xge_mac-master/tbench/verilog/tb_xge_mac.v