强调Verilog代码编写规范，经常是一个不太受欢迎的话题，但却是非常有必要的。

每个代码编写者都有自己的编写习惯，而且都喜欢按照自己的习惯去编写-stressed Verilog code-writing norms, is often not a popular topic, but it is very necessary. Each has its own code writers in the preparation habits, but like their own habits to prepare