文件名称:071162程序
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设计一个用于篮球比赛的定时器。要求:
(1)定时时间为24秒,按递减方式计时,每隔1秒,定时器减1;
(2)定时器的时间用两位数码管显示;
(3)设置两个外部控制开关,开关K1控制定时器的直接复位/启动计时,开关K2控制定时器的暂停/连续计时;当定时器递减计时到零(即定时时间到)时,定时器保持零不变,同时发出报警信号,报警信号用一个发光二极管指示。
(4)输入时钟脉冲的频率为50MHz。
(5)用Verilog HDL语言设计,用Modelsim软件做功能仿真,用Quartus II综合。(Design a basketball game timer. Requirements:
(1) the timing time is 24 seconds, which is timed in a decreasing manner. Every second, the timer is reduced by 1.
(2) the time of the timer is displayed with two digital tubes;
(3) two external control switches are set. Switch K1 controls the direct reset/start time of the timer, and switch K2 controls the pause/continuous time of the timer. When the timer declinates to zero (that is, when the timer time reaches zero), the timer remains unchanged, and an alarm signal is sent at the same time. The alarm signal is indicated by a light-emitting diode.
(4) the input clock pulse frequency is 50MHz.
(5) design with Verilog HDL language, perform function simulation with Modelsim software, and integrate with Quartus II.)
(1)定时时间为24秒,按递减方式计时,每隔1秒,定时器减1;
(2)定时器的时间用两位数码管显示;
(3)设置两个外部控制开关,开关K1控制定时器的直接复位/启动计时,开关K2控制定时器的暂停/连续计时;当定时器递减计时到零(即定时时间到)时,定时器保持零不变,同时发出报警信号,报警信号用一个发光二极管指示。
(4)输入时钟脉冲的频率为50MHz。
(5)用Verilog HDL语言设计,用Modelsim软件做功能仿真,用Quartus II综合。(Design a basketball game timer. Requirements:
(1) the timing time is 24 seconds, which is timed in a decreasing manner. Every second, the timer is reduced by 1.
(2) the time of the timer is displayed with two digital tubes;
(3) two external control switches are set. Switch K1 controls the direct reset/start time of the timer, and switch K2 controls the pause/continuous time of the timer. When the timer declinates to zero (that is, when the timer time reaches zero), the timer remains unchanged, and an alarm signal is sent at the same time. The alarm signal is indicated by a light-emitting diode.
(4) the input clock pulse frequency is 50MHz.
(5) design with Verilog HDL language, perform function simulation with Modelsim software, and integrate with Quartus II.)
相关搜索: fpga
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下载文件列表
文件名 | 大小 | 更新时间 |
---|---|---|
071162程序 | 0 | 2018-07-05 |
071162程序\071162 彭佳丽 | 0 | 2018-07-04 |
071162程序\071162 彭佳丽\原理图.pdsprj | 23621 | 2018-07-04 |
071162程序\071162 彭佳丽\程序 | 0 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\89c52 | 15594 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\89c52.hex | 5973 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\89c52.lnp | 57 | 2018-07-04 |
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071162程序\071162 彭佳丽\程序\89c52.plg | 415 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\89c52.uvopt | 55649 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\89c52.uvproj | 13399 | 2018-07-04 |
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071162程序\071162 彭佳丽\程序\89c52_uvproj.bak | 13233 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\STARTUP.A51 | 6376 | 2009-05-07 |
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071162程序\071162 彭佳丽\程序\test.c | 8866 | 2018-07-04 |
071162程序\071162 彭佳丽\程序\test.LST | 14825 | 2018-07-04 |
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071162程序\071162-武志强 | 0 | 2018-07-04 |
071162程序\071162-武志强\keil | 0 | 2018-07-04 |
071162程序\071162-武志强\keil\ds18b20.c | 2540 | 2018-07-04 |
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071162程序\071162-武志强\keil\lcd1602.c | 3483 | 2018-07-04 |
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071162程序\071162-武志强\keil\main.c | 615 | 2018-07-04 |
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071162程序\071162-武志强\keil\STARTUP.OBJ | 749 | 2018-07-04 |
071162程序\071162-武志强\keil\timer.c | 206 | 2018-07-02 |
071162程序\071162-武志强\keil\timer.h | 135 | 2018-07-04 |
071162程序\071162-武志强\keil\timer.LST | 1161 | 2018-07-04 |
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071162程序\071162-武志强\protues | 0 | 2018-07-04 |
071162程序\071162-武志强\protues\Last Loaded WZQ.DBK | 126083 | 2018-07-04 |
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071162程序\071162-胡珩\keil工程文件\main.c | 10964 | 2018-07-04 |
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071162程序\071162-胡珩\keil工程文件\main.plg | 177 | 2018-07-04 |
071162程序\071162-胡珩\keil工程文件\nongli.h | 15245 | 2018-06-29 |
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071162程序\071162-胡珩\电路仿真图\单片机DS1302多功能电子时钟万年历LCD1602显示.hex | 14998 | 2018-06-29 |
071162程序\严端腾 | 0 | 2018-07-04 |
071162程序\严端腾\1 | 45347 | 2018-07-04 |
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