文件名称:posedge_detect

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2018-04-16
  • 文件大小:
  • 72kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 小明***
  • 相关连接:
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介绍说明--下载内容均来自于网络,请自行研究使用

使能信号往往为一个脉冲,本程序实现对使能信号的检测(The enabling signal is often a pulse. This program realizes the detection of the enabling signal)
相关搜索: verilog
fpga

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
posedge_detect 0 2017-03-30
posedge_detect\posedge_detect.v 2832 2017-03-28
posedge_detect\posedge_detect.v.bak 2812 2017-03-28
posedge_detect\posedge_detect_seg.cr.mti 1265 2017-03-30
posedge_detect\posedge_detect_seg.mpf 80530 2017-03-28
posedge_detect\posedge_detect_seg_top.v 744 2017-03-28
posedge_detect\posedge_detect_seg_top.v.bak 735 2017-03-28
posedge_detect\posedge_detect_seg_top_tb.v 648 2017-03-28
posedge_detect\posedge_detect_seg_top_tb.v.bak 649 2017-03-28
posedge_detect\seg_decode.v 1245 2017-03-27
posedge_detect\transcript 15885 2017-03-28
posedge_detect\vsim.wlf 81920 2017-03-28
posedge_detect\work 0 2017-03-28
posedge_detect\work\_info 2067 2017-03-28
posedge_detect\work\_temp 0 2017-03-28
posedge_detect\work\_temp\vlog0e94w2 424 2017-03-28
posedge_detect\work\_temp\vlog0hsz2v 421 2017-03-28
posedge_detect\work\_temp\vlog0x9s4e 1161 2017-03-28
posedge_detect\work\_temp\vlog18k4kc 423 2017-03-28
posedge_detect\work\_temp\vlog2g5evv 1163 2017-03-28
posedge_detect\work\_temp\vlog4cz4bm 425 2017-03-28
posedge_detect\work\_temp\vlog73krwf 425 2017-03-28
posedge_detect\work\_temp\vlog8vkjn0 1153 2017-03-28
posedge_detect\work\_temp\vlogaj1814 1159 2017-03-28
posedge_detect\work\_temp\vlogb0rihh 424 2017-03-28
posedge_detect\work\_temp\vlogb288tk 420 2017-03-28
posedge_detect\work\_temp\vlogcawx9e 423 2017-03-28
posedge_detect\work\_temp\vlogcdy7sj 1163 2017-03-28
posedge_detect\work\_temp\vlogcsix4w 422 2017-03-28
posedge_detect\work\_temp\vloge5iqdz 422 2017-03-28
posedge_detect\work\_temp\vloghnfqmr 1162 2017-03-28
posedge_detect\work\_temp\vlogm8tnmr 1153 2017-03-28
posedge_detect\work\_temp\vlogmd51h1 1162 2017-03-28
posedge_detect\work\_temp\vlogmdbvn2 421 2017-03-28
posedge_detect\work\_temp\vlogmv21qq 1161 2017-03-28
posedge_detect\work\_temp\vlogqsnv6z 423 2017-03-28
posedge_detect\work\_temp\vlogrivn4g 426 2017-03-28
posedge_detect\work\_temp\vlogrjmnv1 421 2017-03-28
posedge_detect\work\_temp\vlogs9hva9 425 2017-03-28
posedge_detect\work\_temp\vlogvq10ik 426 2017-03-28
posedge_detect\work\_temp\vlogxfff4m 1152 2017-03-28
posedge_detect\work\_temp\vlogy21tce 1162 2017-03-28
posedge_detect\work\_temp\vlogyc7mvq 421 2017-03-28
posedge_detect\work\_temp\vlogynxtiw 421 2017-03-28
posedge_detect\work\_temp\vlogzyvt1h 422 2017-03-28
posedge_detect\work\_vmake 26 2017-03-28
posedge_detect\work\posedge_detect 0 2017-03-28
posedge_detect\work\posedge_detect\_primary.dat 1391 2017-03-28
posedge_detect\work\posedge_detect\_primary.dbs 1368 2017-03-28
posedge_detect\work\posedge_detect\_primary.vhd 924 2017-03-28
posedge_detect\work\posedge_detect\verilog.asm 12992 2017-03-28
posedge_detect\work\posedge_detect\verilog.rw 538 2017-03-28
posedge_detect\work\posedge_detect_seg_top 0 2017-03-28
posedge_detect\work\posedge_detect_seg_top\_primary.dat 662 2017-03-28
posedge_detect\work\posedge_detect_seg_top\_primary.dbs 818 2017-03-28
posedge_detect\work\posedge_detect_seg_top\_primary.vhd 373 2017-03-28
posedge_detect\work\posedge_detect_seg_top\verilog.asm 4576 2017-03-28
posedge_detect\work\posedge_detect_seg_top\verilog.rw 111 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb 0 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb\_primary.dat 593 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb\_primary.dbs 877 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb\_primary.vhd 110 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb\verilog.asm 5856 2017-03-28
posedge_detect\work\posedge_detect_seg_top_tb\verilog.rw 551 2017-03-28
posedge_detect\work\seg_decode 0 2017-03-28
posedge_detect\work\seg_decode\_primary.dat 1424 2017-03-28
posedge_detect\work\seg_decode\_primary.dbs 1145 2017-03-28
posedge_detect\work\seg_decode\_primary.vhd 306 2017-03-28
posedge_detect\work\seg_decode\verilog.asm 6776 2017-03-28
posedge_detect\work\seg_decode\verilog.rw 342 2017-03-28

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