文件名称:verilog2vhdl

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [C/C++]
  • 上传时间:
  • 2018-04-18
  • 文件大小:
  • 22.32mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • nos***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Verilog2C++ translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.
相关搜索: verilog
hdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
verilog2vhdl 0 2013-04-11
verilog2vhdl\11APR2013 0 2013-02-10
verilog2vhdl\11APR2013\bin 0 2013-03-09
verilog2vhdl\11APR2013\bin\verilog2vhdl 1012 2013-02-13
verilog2vhdl\11APR2013\bin\verilog2vhdl.bat 863 2013-02-08
verilog2vhdl\11APR2013\bin\verilog2vhdlcomponent 1028 2013-02-13
verilog2vhdl\11APR2013\bin\verilog2vhdlcomponent.bat 863 2013-02-08
verilog2vhdl\11APR2013\bin\verilog2vhdlentity 1023 2013-02-13
verilog2vhdl\11APR2013\bin\verilog2vhdlentity.bat 876 2013-02-08
verilog2vhdl\11APR2013\examples 0 2012-02-04
verilog2vhdl\11APR2013\examples\simple_and 0 2012-12-23
verilog2vhdl\11APR2013\examples\simple_and\runme.bat 69 2012-12-01
verilog2vhdl\11APR2013\examples\simple_and\runme.csh 84 2012-11-30
verilog2vhdl\11APR2013\examples\simple_and\simple_and.v 804 2012-02-04
verilog2vhdl\11APR2013\lib 0 2013-02-10
verilog2vhdl\11APR2013\lib\designplayer.jar 24014332 2013-04-11
verilog2vhdl\11APR2013\LICENSE.txt 1424 2013-02-09
verilog2vhdl\11APR2013\README.txt 1423 2012-12-02
verilog2vhdl\11APR2013\setup_env.bat 183 2013-02-13
verilog2vhdl\11APR2013\setup_env.csh 800 2013-02-13
verilog2vhdl\11APR2013\setup_env.sh 825 2013-02-13
verilog2vhdl\11APR2013\vhdl_pkgs 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex\body.dmp 219395 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex\math_complex.dmp 49871 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real\body.dmp 137863 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real\math_real.dmp 29820 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit\body.dmp 345296 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit\numeric_bit.dmp 63299 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std\body.dmp 515667 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std\numeric_std.dmp 98095 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164\body.dmp 172202 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164\std_logic_1164.dmp 37673 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith\body.dmp 407247 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith\std_logic_arith.dmp 105522 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith_ext 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith_ext\body.dmp 267941 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith_ext\std_logic_arith_ext.dmp 85460 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_misc 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_misc\body.dmp 212059 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_misc\std_logic_misc.dmp 66103 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_signed 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_signed\body.dmp 201518 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_signed\std_logic_signed.dmp 164118 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_textio 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_textio\body.dmp 194265 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_textio\std_logic_textio.dmp 90457 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_unsigned 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_unsigned\body.dmp 199160 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_unsigned\std_logic_unsigned.dmp 163627 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\vital_primitives 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\vital_primitives\vital_primitives.dmp 216666 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\vital_timing 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\vital_timing\body.dmp 333243 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\vital_timing\vital_timing.dmp 94081 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_negedge_clk 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_negedge_clk\dff_async_negedge_rst_negedge_clk.dmp 55985 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_negedge_clk\rtl.dmp 57434 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_posedge_clk 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_posedge_clk\dff_async_negedge_rst_posedge_clk.dmp 58622 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_negedge_rst_posedge_clk\rtl.dmp 59971 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_negedge_clk 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_negedge_clk\dff_async_posedge_rst_negedge_clk.dmp 61159 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_negedge_clk\rtl.dmp 62508 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_posedge_clk 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_posedge_clk\dff_async_posedge_rst_posedge_clk.dmp 63696 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_async_posedge_rst_posedge_clk\rtl.dmp 65045 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_negedge 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_negedge\dff_simple_negedge.dmp 53939 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_negedge\rtl.dmp 54797 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_posedge 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_posedge\dff_simple_posedge.dmp 50807 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\dff_simple_posedge\rtl.dmp 53071 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_and 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_and\fvp_prim_and.dmp 50802 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_and\rtl.dmp 52397 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_buf 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif0 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif0\fvp_prim_bufif0.dmp 61312 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif0\rtl.dmp 62154 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif1 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif1\fvp_prim_bufif1.dmp 63012 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_bufif1\rtl.dmp 63705 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_buf\fvp_prim_buf.dmp 60048 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_buf\rtl.dmp 60454 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_cmos 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_cmos\fvp_prim_cmos.dmp 78256 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_cmos\rtl.dmp 81357 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_nand 0 2013-02-10
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_nand\fvp_prim_nand.dmp 53251 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_nand\rtl.dmp 53809 2013-04-06
verilog2vhdl\11APR2013\vhdl_pkgs\lib\misc\fvp_prim_nmos 0 2013-02-10

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