文件名称:at7_ex03

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2018-04-09
  • 文件大小:
  • 721kb
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  • 0次
  • 提 供 者:
  • 2***
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使用FPGA内部的PLL产生时钟,计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
相关搜索: verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
at7_ex03\at7.cache\wt\java_command_handlers.wdf 1643 2017-04-01
at7_ex03\at7.cache\wt\project.wpc 121 2017-04-01
at7_ex03\at7.cache\wt\synthesis.wdf 5233 2017-04-01
at7_ex03\at7.cache\wt\synthesis_details.wdf 100 2017-04-01
at7_ex03\at7.cache\wt\webtalk_pa.xml 3443 2017-04-01
at7_ex03\at7.hw\at7.lpr 343 2017-04-01
at7_ex03\at7.hw\hw_1\hw.xml 683 2017-04-01
at7_ex03\at7.hw\webtalk\.xsim_webtallk.info 59 2017-02-22
at7_ex03\at7.hw\webtalk\labtool_webtalk.log 372 2017-02-22
at7_ex03\at7.hw\webtalk\usage_statistics_ext_labtool.html 2894 2017-02-22
at7_ex03\at7.hw\webtalk\usage_statistics_ext_labtool.xml 2460 2017-02-22
at7_ex03\at7.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo 3987 2017-02-09
at7_ex03\at7.ip_user_files\ip\clk_wiz_0\clk_wiz_0_stub.v 1347 2017-02-09
at7_ex03\at7.ip_user_files\ip\clk_wiz_0\clk_wiz_0_stub.vhdl 1322 2017-02-09
at7_ex03\at7.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh 24240 2017-02-07
at7_ex03\at7.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_pll.vh 19041 2017-02-07
at7_ex03\at7.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_mmcm.vh 24226 2017-02-07
at7_ex03\at7.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_pll.vh 22052 2017-02-07
at7_ex03\at7.ip_user_files\README.txt 130 2017-02-07
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.sh 4307 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.udo 0 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\compile.do 715 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\file_info.txt 762 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\simulate.do 320 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\activehdl\wave.do 32 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\ies\clk_wiz_0.sh 5581 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\ies\file_info.txt 798 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\ies\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\ies\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\ies\run.f 422 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.sh 4611 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.udo 0 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\compile.do 702 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\file_info.txt 762 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\simulate.do 311 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\modelsim\wave.do 32 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.sh 4728 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.udo 0 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\compile.do 686 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\elaborate.do 183 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\file_info.txt 762 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\simulate.do 195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\questa\wave.do 32 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\README.txt 3236 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.sh 4306 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.udo 0 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\compile.do 705 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\file_info.txt 762 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\simulate.do 320 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\riviera\wave.do 32 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\vcs\clk_wiz_0.sh 6874 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\vcs\file_info.txt 798 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\vcs\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\vcs\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\vcs\simulate.do 11 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\clk_wiz_0.sh 3947 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\cmd.tcl 464 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\elab.opt 188 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\file_info.txt 798 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\glbl.v 1470 2016-06-02
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\README.txt 2195 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\vhdl.prj 73 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\vlog.prj 432 2017-02-09
at7_ex03\at7.ip_user_files\sim_scripts\clk_wiz_0\xsim\xsim.ini 58 2017-02-09
at7_ex03\at7.runs\.jobs\vrs_config_1.xml 216 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_10.xml 419 2017-04-01
at7_ex03\at7.runs\.jobs\vrs_config_2.xml 416 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_3.xml 216 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_4.xml 230 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_5.xml 236 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_6.xml 216 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_7.xml 230 2017-02-07
at7_ex03\at7.runs\.jobs\vrs_config_8.xml 236 2017-02-09
at7_ex03\at7.runs\.jobs\vrs_config_9.xml 419 2017-02-22
at7_ex03\at7.runs\clk_wiz_0_synth_1\.vivado.begin.rst 177 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\.vivado.end.rst 0 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\.Vivado_Synthesis.queue.rst 0 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\.Xil\clk_wiz_0_propImpl.xdc 405 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\clk_wiz_0.dcp 12631 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\clk_wiz_0.tcl 3991 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\clk_wiz_0.vds 23819 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\clk_wiz_0_utilization_synth.pb 231 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\clk_wiz_0_utilization_synth.rpt 7427 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\dont_touch.xdc 2161 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\gen_run.xml 1752 2017-04-01
at7_ex03\at7.runs\clk_wiz_0_synth_1\htr.txt 379 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\ISEWrap.js 7308 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\ISEWrap.sh 1720 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\project.wdf 3779 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\rundef.js 1309 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\runme.bat 229 2017-02-09
at7_ex03\at7.runs\clk_wiz_0_synth_1\runme.log 23798 2017-02-09

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