文件名称:uart_55x_lite
- 所属分类:
- VHDL编程
- 资源属性:
- 上传时间:
- 2018-04-09
- 文件大小:
- 35kb
- 下载次数:
- 0次
- 提 供 者:
- fengy******
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
本模块设计仿照ST16C554芯片,特点如下:
a) Localbus总线接口;
b) 多通道设计,最大通道数为4,实际通道数可配置;
c) 两种中断方式,支持电平中断、沿中断;(The module is designed and modeled on ST16C554 chip.
A) Localbus bus interface;
B) multi-channel design. The maximum number of channels is 4, and the number of actual channels is configurable.
C) two interrupt modes, supporting level interruption and interruption.)
a) Localbus总线接口;
b) 多通道设计,最大通道数为4,实际通道数可配置;
c) 两种中断方式,支持电平中断、沿中断;(The module is designed and modeled on ST16C554 chip.
A) Localbus bus interface;
B) multi-channel design. The maximum number of channels is 4, and the number of actual channels is configurable.
C) two interrupt modes, supporting level interruption and interruption.)
相关搜索: verilog
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下载文件列表
文件名 | 大小 | 更新时间 |
---|---|---|
uart_55x_lite | 0 | 2016-06-14 |
uart_55x_lite\greybox_tmp | 0 | 2016-06-14 |
uart_55x_lite\greybox_tmp\cbx_args.txt | 482 | 2015-04-15 |
uart_55x_lite\pll_30m_in.qip | 0 | 2015-04-15 |
uart_55x_lite\sdpram_dxw8.qip | 0 | 2015-04-15 |
uart_55x_lite\uart_55x_lite.v | 23054 | 2016-06-13 |
uart_55x_lite\uart_55x_lite.v.bak | 23048 | 2016-05-06 |
uart_55x_lite\uart_baud_gen.v | 3035 | 2014-09-02 |
uart_55x_lite\uart_channel.v | 20075 | 2016-06-28 |
uart_55x_lite\uart_channel.v.bak | 20073 | 2015-04-27 |
uart_55x_lite\uart_driver.v | 6649 | 2014-02-19 |
uart_55x_lite\uart_fifoarbiter.v | 13074 | 2014-02-19 |
uart_55x_lite\uart_intc.v | 6240 | 2014-02-19 |
uart_55x_lite\uart_receive.v | 15075 | 2016-06-26 |
uart_55x_lite\uart_regs.v | 32734 | 2016-06-28 |
uart_55x_lite\uart_regs.v.bak | 32697 | 2014-09-28 |
uart_55x_lite\uart_rxfifo_if.v | 17450 | 2014-09-02 |
uart_55x_lite\uart_send.v | 9863 | 2014-02-18 |
uart_55x_lite\uart_txfifo_if.v | 20345 | 2014-09-02 |