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test60_TRIGD\component\work\tb_top\tb_top.vhd

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test60_TRIGD\constraint

test60_TRIGD\coreconsole

test60_TRIGD\designer

test60_TRIGD\designer\impl1

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test60_TRIGD\designer\impl1\simulation

test60_TRIGD\designer\impl1\TRIGD.ide_des

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test60_TRIGD\hdl

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test60_TRIGD\simulation

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test60_TRIGD\simulation\postsynth

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test60_TRIGD\simulation\postsynth\_lib1_0.qdb

test60_TRIGD\simulation\postsynth\_lib1_0.qpg

test60_TRIGD\simulation\postsynth\_lib1_0.qtl

test60_TRIGD\simulation\postsynth\_vmake

test60_TRIGD\simulation\run.do

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test60_TRIGD\simulation\vsim.wlf

test60_TRIGD\smartgen

test60_TRIGD\smartgen\smartgen.aws

test60_TRIGD\smartgen\tb_top_work.ixf

test60_TRIGD\stimulus

test60_TRIGD\stimulus\tb_clk.vhd

test60_TRIGD\synthesis

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test60_TRIGD\synthesis\backup

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test60_TRIGD\synthesis\coreip

test60_TRIGD\synthesis\dm

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test60_TRIGD\synthesis\scratchproject.prs

test60_TRIGD\synthesis\synlog.tcl

test60_TRIGD\synthesis\synlog

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test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_area_report.xml

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test60_TRIGD\synthesis\synlog\report\TRIGD_premap_warnings.txt

test60_TRIGD\synthesis\synlog\syntax_constraint_check.rpt.rptmap

test60_TRIGD\synthesis\synlog\TRIGD_compiler.srr

test60_TRIGD\synthesis\synlog\TRIGD_compiler.srr.rptmap

test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.srr

test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.szr

test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.xck

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test60_TRIGD\synthesis\synlog\TRIGD_premap.srr

test60_TRIGD\synthesis\synlog\TRIGD_premap.szr

test60_TRIGD\synthesis\synplify.log

test60_TRIGD\synthesis\syntmp

test60_TRIGD\synthesis\syntmp\closed.png

test60_TRIGD\synthesis\syntmp\cmdrec_compiler.log

test60_TRIGD\synthesis\syntmp\cmdrec_fpga_mapper.log

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test60_TRIGD\synthesis\syntmp\cmdrec_premap.log

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test60_TRIGD\synthesis\synwork\layer0.srs

test60_TRIGD\synthesis\synwork\layer0.tlg

test60_TRIGD\synthesis\synwork\TRIGD_comp.fdep

test60_TRIGD\synthesis\synwork\TRIGD_comp.srs

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