test59_TRIGU\component

test59_TRIGU\component\work

test59_TRIGU\component\work\DESIGN_FIRMWARE

test59_TRIGU\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf

test59_TRIGU\component\work\tb_top

test59_TRIGU\component\work\tb_top\tb_top.cxf

test59_TRIGU\component\work\tb_top\tb_top.sdb

test59_TRIGU\component\work\tb_top\tb_top.vhd

test59_TRIGU\component\work\tb_top\tb_top_manifest.txt

test59_TRIGU\constraint

test59_TRIGU\coreconsole

test59_TRIGU\designer

test59_TRIGU\designer\impl1

test59_TRIGU\designer\impl1\designer_synth_check.log

test59_TRIGU\designer\impl1\simulation

test59_TRIGU\designer\impl1\TRIGU.ide_des

test59_TRIGU\designer\impl1\TRIGU.tcl

test59_TRIGU\hdl

test59_TRIGU\hdl\TRIGU.vhd

test59_TRIGU\simulation

test59_TRIGU\simulation\modelsim.ini

test59_TRIGU\simulation\modelsim.ini.sav

test59_TRIGU\simulation\postsynth

test59_TRIGU\simulation\postsynth\_info

test59_TRIGU\simulation\postsynth\_lib.qdb

test59_TRIGU\simulation\postsynth\_lib1_0.qdb

test59_TRIGU\simulation\postsynth\_lib1_0.qpg

test59_TRIGU\simulation\postsynth\_lib1_0.qtl

test59_TRIGU\simulation\postsynth\_vmake

test59_TRIGU\simulation\run.do

test59_TRIGU\simulation\tb_top_postsynth_simulation.log

test59_TRIGU\simulation\vsim.wlf

test59_TRIGU\smartgen

test59_TRIGU\smartgen\DESIGN_FIRMWARE_work.ixf

test59_TRIGU\smartgen\smartgen.aws

test59_TRIGU\smartgen\tb_top_work.ixf

test59_TRIGU\stimulus

test59_TRIGU\stimulus\tb_clk.vhd

test59_TRIGU\synthesis

test59_TRIGU\synthesis\.recordref

test59_TRIGU\synthesis\backup

test59_TRIGU\synthesis\backup\TRIGU.srr

test59_TRIGU\synthesis\coreip

test59_TRIGU\synthesis\dm

test59_TRIGU\synthesis\dm\layer0.xdm

test59_TRIGU\synthesis\run_options.txt

test59_TRIGU\synthesis\scratchproject.prs

test59_TRIGU\synthesis\synlog.tcl

test59_TRIGU\synthesis\synlog

test59_TRIGU\synthesis\synlog\layer0.tlg.rptmap

test59_TRIGU\synthesis\synlog\report

test59_TRIGU\synthesis\synlog\report\TRIGU_compiler_notes.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_compiler_runstatus.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_area_report.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_combined_clk.rpt

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_errors.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_notes.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_opt_report.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_resourceusage.rpt

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_runstatus.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_timing_report.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_fpga_mapper_warnings.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_premap_errors.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_premap_notes.txt

test59_TRIGU\synthesis\synlog\report\TRIGU_premap_runstatus.xml

test59_TRIGU\synthesis\synlog\report\TRIGU_premap_warnings.txt

test59_TRIGU\synthesis\synlog\syntax_constraint_check.rpt.rptmap

test59_TRIGU\synthesis\synlog\TRIGU_compiler.srr

test59_TRIGU\synthesis\synlog\TRIGU_compiler.srr.rptmap

test59_TRIGU\synthesis\synlog\TRIGU_fpga_mapper.srr

test59_TRIGU\synthesis\synlog\TRIGU_fpga_mapper.szr

test59_TRIGU\synthesis\synlog\TRIGU_fpga_mapper.xck

test59_TRIGU\synthesis\synlog\TRIGU_multi_srs_gen.srr

test59_TRIGU\synthesis\synlog\TRIGU_premap.srr

test59_TRIGU\synthesis\synlog\TRIGU_premap.szr

test59_TRIGU\synthesis\synplify.log

test59_TRIGU\synthesis\syntmp

test59_TRIGU\synthesis\syntmp\closed.png

test59_TRIGU\synthesis\syntmp\cmdrec_compiler.log

test59_TRIGU\synthesis\syntmp\cmdrec_fpga_mapper.log

test59_TRIGU\synthesis\syntmp\cmdrec_multi_srs_gen.log

test59_TRIGU\synthesis\syntmp\cmdrec_premap.log

test59_TRIGU\synthesis\syntmp\open.png

test59_TRIGU\synthesis\syntmp\run_option.xml

test59_TRIGU\synthesis\syntmp\statusReport.html

test59_TRIGU\synthesis\syntmp\TRIGU.plg

test59_TRIGU\synthesis\syntmp\TRIGU_srr.htm

test59_TRIGU\synthesis\syntmp\TRIGU_toc.htm

test59_TRIGU\synthesis\synwork

test59_TRIGU\synthesis\synwork\.cckTransfer

test59_TRIGU\synthesis\synwork\_mh_info

test59_TRIGU\synthesis\synwork\layer0.fdep

test59_TRIGU\synthesis\synwork\layer0.fdeporig

test59_TRIGU\synthesis\synwork\layer0.srs

test59_TRIGU\synthesis\synwork\layer0.tlg

test59_TRIGU\synthesis\synwork\TRIGU_comp.fdep

test59_TRIGU\synthesis\synwork\TRIGU_comp.srs

test59_TRIGU\synthesis\synwork\TRIGU_m.srm

test59_TRIGU\synthesis\synwork\TRIGU_m_srm

test59_TRIGU\synthesis\synwork\TRIGU_m_srm\fileinfo.srm