bch_verilog-master

bch_verilog-master\.gitignore

bch_verilog-master\COPYING

bch_verilog-master\Makefile

bch_verilog-master\Makefile.xilinx

bch_verilog-master\README

bch_verilog-master\bch.vh

bch_verilog-master\bch_blank_ecc.v

bch_verilog-master\bch_chien.v

bch_verilog-master\bch_decoder.v

bch_verilog-master\bch_defs.vh

bch_verilog-master\bch_encode.v

bch_verilog-master\bch_encode.vh

bch_verilog-master\bch_error_dec.v

bch_verilog-master\bch_error_one.v

bch_verilog-master\bch_error_tmec.v

bch_verilog-master\bch_math.v

bch_verilog-master\bch_params.vh

bch_verilog-master\bch_sigma_bma_noinv.v

bch_verilog-master\bch_sigma_bma_parallel.v

bch_verilog-master\bch_sigma_bma_serial.v

bch_verilog-master\bch_syndrome.v

bch_verilog-master\bch_syndrome.vh

bch_verilog-master\bch_syndrome_method1.v

bch_verilog-master\bch_syndrome_method2.v

bch_verilog-master\benchmark

bch_verilog-master\benchmark\xilinx_decoder.sh

bch_verilog-master\benchmark\xilinx_decoder.v

bch_verilog-master\benchmark\xilinx_encode.sh

bch_verilog-master\benchmark\xilinx_encode.v

bch_verilog-master\benchmark\xilinx_error_dec.sh

bch_verilog-master\benchmark\xilinx_error_dec.v

bch_verilog-master\benchmark\xilinx_error_one.sh

bch_verilog-master\benchmark\xilinx_error_one.v

bch_verilog-master\benchmark\xilinx_error_tmec.sh

bch_verilog-master\benchmark\xilinx_error_tmec.v

bch_verilog-master\benchmark\xilinx_inverter.sh

bch_verilog-master\benchmark\xilinx_inverter.v

bch_verilog-master\benchmark\xilinx_mdecoder.sh

bch_verilog-master\benchmark\xilinx_mdecoder.v

bch_verilog-master\benchmark\xilinx_noinv.sh

bch_verilog-master\benchmark\xilinx_noinv.v

bch_verilog-master\benchmark\xilinx_parallel.sh

bch_verilog-master\benchmark\xilinx_parallel.v

bch_verilog-master\benchmark\xilinx_serial.sh

bch_verilog-master\benchmark\xilinx_serial.v

bch_verilog-master\benchmark\xilinx_syndrome.sh

bch_verilog-master\benchmark\xilinx_syndrome.v

bch_verilog-master\compare_cla.v

bch_verilog-master\config.vh

bch_verilog-master\log2.vh

bch_verilog-master\matrix.v

bch_verilog-master\matrix.vh

bch_verilog-master\scripts

bch_verilog-master\scripts\benchmark.sh

bch_verilog-master\scripts\makedeps.sh

bch_verilog-master\sim.v

bch_verilog-master\tb_basis.v

bch_verilog-master\tb_inverter.v

bch_verilog-master\tb_mult.v

bch_verilog-master\tb_sim.v

bch_verilog-master\util.v

bch_verilog-master\xilinx.ucf