FPGA_Based_CNN-master

FPGA_Based_CNN-master\.gitignore

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\filters.xml

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\mem_system.xml

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\mem_system_schematic.nlv

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system.xml

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system_schematic.nlv

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\preferences.xml

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\Clock_hw.tcl

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.SDC

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.dpf

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.htm

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qpf

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qsf

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.sld

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator_assignment_defaults.qdf

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\avalon_bridge.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\avalon_bridge_hw.tcl

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\bit_width.vh

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cent_ctrl.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cent_ctrl_hw.tcl

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\clock.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cnn_parameters.vh

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\conv.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\conv_old.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\db

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.db_info

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.sld_design_entry.sci

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\fifo_v2.qip

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\fifo_v2.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ifm_loader.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_state_actions.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_state_machine.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_states.vh

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_init.mif

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system.qsys

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system.sopcinfo

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_all_pins.txt

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_summary.csv

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export2.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export2_hw.tcl

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export_hw.tcl

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\new_rtl_netlist

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ofm_loader.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ofm_wb.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\old_rtl_netlist

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\parameters.vh

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pcie_system.qsys

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pcie_system.sopcinfo

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.qip

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.qip

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\read_state_actions.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\read_states.vh

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\rom_script.py

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\serv_req_info.txt

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\toSevenSeg.v

FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\weight_loader.v

FPGA_Based_CNN-master\README.md

FPGA_Based_CNN-master\Using the User Application.pdf

FPGA_Based_CNN-master\pcie_linux_driver

FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.ko.cmd

FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.mod.o.cmd

FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.o.cmd

FPGA_Based_CNN-master\pcie_linux_driver\.built-in.o.cmd

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-0Y4HMY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-2BLFMY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-AXCMMY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-O215MY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-QK7EMY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-QPOYMY

FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-RQCNMY

FPGA_Based_CNN-master\pcie_linux_driver\.tmp_versions

FPGA_Based_CNN-master\pcie_linux_driver\.tmp_versions\altera_dma.mod

FPGA_Based_CNN-master\pcie_linux_driver\Makefile

FPGA_Based_CNN-master\pcie_linux_driver\Module.symvers

FPGA_Based_CNN-master\pcie_linux_driver\README

FPGA_Based_CNN-master\pcie_linux_driver\altera.dma.hmc

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.c

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.cmc

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.h

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.ko

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.ko.unsigned

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.mod.c

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.mod.o

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.o

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.tmp_c

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma_cmd.h

FPGA_Based_CNN-master\pcie_linux_driver\altera_dma_load

FPGA_Based_CNN-master\pcie_linux_driver\built-in.o

FPGA_Based_CNN-master\pcie_linux_driver\genRandData.py

FPGA_Based_CNN-master\pcie_linux_driver\install

FPGA_Based_CNN-master\pcie_linux_driver\modules.order

FPGA_Based_CNN-master\pcie_linux_driver\run