UART.pdf

Verilog HDL

Verilog HDL\bps_rx.v

Verilog HDL\bps_rx.v.bak

Verilog HDL\db

Verilog HDL\db\logic_util_heursitic.dat

Verilog HDL\db\PLL_CLK_altpll.v

Verilog HDL\db\prev_cmp_uart.qmsg

Verilog HDL\db\uart.ace_cmp.bpm

Verilog HDL\db\uart.ace_cmp.cdb

Verilog HDL\db\uart.ace_cmp.hdb

Verilog HDL\db\uart.asm.qmsg

Verilog HDL\db\uart.asm.rdb

Verilog HDL\db\uart.asm_labs.ddb

Verilog HDL\db\uart.atom_map.rvd

Verilog HDL\db\uart.cbx.xml

Verilog HDL\db\uart.cmp.bpm

Verilog HDL\db\uart.cmp.cdb

Verilog HDL\db\uart.cmp.hdb

Verilog HDL\db\uart.cmp.idb

Verilog HDL\db\uart.cmp.kpt

Verilog HDL\db\uart.cmp.logdb

Verilog HDL\db\uart.cmp.rdb

Verilog HDL\db\uart.cmp_merge.kpt

Verilog HDL\db\uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

Verilog HDL\db\uart.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

Verilog HDL\db\uart.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

Verilog HDL\db\uart.db_info

Verilog HDL\db\uart.eco.cdb

Verilog HDL\db\uart.eda.qmsg

Verilog HDL\db\uart.fit.qmsg

Verilog HDL\db\uart.hier_info

Verilog HDL\db\uart.hif

Verilog HDL\db\uart.ipinfo

Verilog HDL\db\uart.lpc.html

Verilog HDL\db\uart.lpc.rdb

Verilog HDL\db\uart.lpc.txt

Verilog HDL\db\uart.map.ammdb

Verilog HDL\db\uart.map.bpm

Verilog HDL\db\uart.map.cdb

Verilog HDL\db\uart.map.hdb

Verilog HDL\db\uart.map.kpt

Verilog HDL\db\uart.map.logdb

Verilog HDL\db\uart.map.qmsg

Verilog HDL\db\uart.map.rdb

Verilog HDL\db\uart.map_bb.cdb

Verilog HDL\db\uart.map_bb.hdb

Verilog HDL\db\uart.map_bb.logdb

Verilog HDL\db\uart.pplq.rdb

Verilog HDL\db\uart.pre_map.hdb

Verilog HDL\db\uart.pti_db_list.ddb

Verilog HDL\db\uart.qns

Verilog HDL\db\uart.root_partition.map.reg_db.cdb

Verilog HDL\db\uart.routing.rdb

Verilog HDL\db\uart.rpp.qmsg

Verilog HDL\db\uart.rtlv.hdb

Verilog HDL\db\uart.rtlv_sg.cdb

Verilog HDL\db\uart.rtlv_sg_swap.cdb

Verilog HDL\db\uart.sgate.rvd

Verilog HDL\db\uart.sgate_sm.rvd

Verilog HDL\db\uart.sgdiff.cdb

Verilog HDL\db\uart.sgdiff.hdb

Verilog HDL\db\uart.sld_design_entry.sci

Verilog HDL\db\uart.sld_design_entry_dsc.sci

Verilog HDL\db\uart.smart_action.txt

Verilog HDL\db\uart.sta.qmsg

Verilog HDL\db\uart.sta.rdb

Verilog HDL\db\uart.sta_cmp.8_slow_1200mv_85c.tdb

Verilog HDL\db\uart.syn_hier_info

Verilog HDL\db\uart.tis_db_list.ddb

Verilog HDL\db\uart.tiscmp.fast_1200mv_0c.ddb

Verilog HDL\db\uart.tiscmp.fastest_slow_1200mv_0c.ddb

Verilog HDL\db\uart.tiscmp.fastest_slow_1200mv_85c.ddb

Verilog HDL\db\uart.tiscmp.slow_1200mv_0c.ddb

Verilog HDL\db\uart.tiscmp.slow_1200mv_85c.ddb

Verilog HDL\db\uart.vpr.ammdb

Verilog HDL\greybox_tmp

Verilog HDL\greybox_tmp\cbx_args.txt

Verilog HDL\incremental_db

Verilog HDL\incremental_db\compiled_partitions

Verilog HDL\incremental_db\compiled_partitions\uart.db_info

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.ammdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.cdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.dfp

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.hdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.kpt

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.logdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.cmp.rcfdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.cdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.dpi

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.cdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hb_info

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.sig

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.hdb

Verilog HDL\incremental_db\compiled_partitions\uart.root_partition.map.kpt

Verilog HDL\incremental_db\README

Verilog HDL\PLL_CLK.ppf

Verilog HDL\PLL_CLK.qip

Verilog HDL\PLL_CLK.v