文件名称:AD9512_ISE
介绍说明－－下载内容均来自于网络，请自行研究使用
AD9512提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.)
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下载文件列表
AD9512
AD9512\AD9512_0923.gise
AD9512\AD9512_0923.xise
AD9512\CSB.mif
AD9512\CSB_226.mif
AD9512\DCM_10M.tfi
AD9512\DCM_10M.v
AD9512\DCM_10M_arwz.ucf
AD9512\SDIO.mif
AD9512\SDIO_226.mif
AD9512\_ngo
AD9512\_ngo\netlist.lst
AD9512\_xmsgs
AD9512\_xmsgs\bitgen.xmsgs
AD9512\_xmsgs\map.xmsgs
AD9512\_xmsgs\ngdbuild.xmsgs
AD9512\_xmsgs\par.xmsgs
AD9512\_xmsgs\pn_parser.xmsgs
AD9512\_xmsgs\trce.xmsgs
AD9512\_xmsgs\xst.xmsgs
AD9512\blk_mem_gen_v6_3.mif
AD9512\ipcore_dir
AD9512\ipcore_dir\CSB
AD9512\ipcore_dir\CSB\example_design
AD9512\ipcore_dir\CSB\example_design\CSB_top.ucf
AD9512\ipcore_dir\CSB\example_design\CSB_top.vhd
AD9512\ipcore_dir\CSB\example_design\CSB_top.xdc
AD9512\ipcore_dir\CSB\example_design\bmg_wrapper.vhd
AD9512\ipcore_dir\CSB\implement
AD9512\ipcore_dir\CSB\implement\implement.bat
AD9512\ipcore_dir\CSB\implement\implement.sh
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.bat
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.sh
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.tcl
AD9512\ipcore_dir\CSB\implement\xst.prj
AD9512\ipcore_dir\CSB\implement\xst.scr
AD9512\ipcore_dir\CSB\simulation
AD9512\ipcore_dir\CSB\simulation\addr_gen.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_stim_gen.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_pkg.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_synth.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_top.vhd
AD9512\ipcore_dir\CSB\simulation\functional
AD9512\ipcore_dir\CSB\simulation\functional\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB\simulation\functional\simulate_isim.bat
AD9512\ipcore_dir\CSB\simulation\functional\simulate_mti.do
AD9512\ipcore_dir\CSB\simulation\functional\simulate_ncsim.sh
AD9512\ipcore_dir\CSB\simulation\functional\wave_mti.do
AD9512\ipcore_dir\CSB\simulation\functional\wave_ncsim.sv
AD9512\ipcore_dir\CSB\simulation\random.vhd
AD9512\ipcore_dir\CSB\simulation\timing
AD9512\ipcore_dir\CSB\simulation\timing\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB\simulation\timing\simulate_isim.bat
AD9512\ipcore_dir\CSB\simulation\timing\simulate_mti.do
AD9512\ipcore_dir\CSB\simulation\timing\simulate_ncsim.sh
AD9512\ipcore_dir\CSB\simulation\timing\wave_mti.do
AD9512\ipcore_dir\CSB\simulation\timing\wave_ncsim.sv
AD9512\ipcore_dir\CSB.asy
AD9512\ipcore_dir\CSB.gise
AD9512\ipcore_dir\CSB.mif
AD9512\ipcore_dir\CSB.ngc
AD9512\ipcore_dir\CSB.sym
AD9512\ipcore_dir\CSB.v
AD9512\ipcore_dir\CSB.veo
AD9512\ipcore_dir\CSB.xco
AD9512\ipcore_dir\CSB.xise
AD9512\ipcore_dir\CSB_226
AD9512\ipcore_dir\CSB_226\example_design
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.ucf
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.vhd
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.xdc
AD9512\ipcore_dir\CSB_226\example_design\bmg_wrapper.vhd
AD9512\ipcore_dir\CSB_226\implement
AD9512\ipcore_dir\CSB_226\implement\implement.bat
AD9512\ipcore_dir\CSB_226\implement\implement.sh
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.bat
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.sh
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.tcl
AD9512\ipcore_dir\CSB_226\implement\xst.prj
AD9512\ipcore_dir\CSB_226\implement\xst.scr
AD9512\ipcore_dir\CSB_226\simulation
AD9512\ipcore_dir\CSB_226\simulation\addr_gen.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_stim_gen.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_pkg.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_synth.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_top.vhd
AD9512\ipcore_dir\CSB_226\simulation\functional
AD9512\ipcore_dir\CSB_226\simulation\functional\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_isim.bat
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_mti.do
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_ncsim.sh
AD9512\ipcore_dir\CSB_226\simulation\functional\wave_mti.do
AD9512\ipcore_dir\CSB_226\simulation\functional\wave_ncsim.sv
AD9512\ipcore_dir\CSB_226\simulation\random.vhd
AD9512\ipcore_dir\CSB_226\simulation\timing
AD9512\ipcore_dir\CSB_226\simulation\timing\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_isim.bat
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_mti.do
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_ncsim.sh
AD9512\ipcore_dir\CSB_226\simulation\timing\wave_mti.do
AD9512\AD9512_0923.gise
AD9512\AD9512_0923.xise
AD9512\CSB.mif
AD9512\CSB_226.mif
AD9512\DCM_10M.tfi
AD9512\DCM_10M.v
AD9512\DCM_10M_arwz.ucf
AD9512\SDIO.mif
AD9512\SDIO_226.mif
AD9512\_ngo
AD9512\_ngo\netlist.lst
AD9512\_xmsgs
AD9512\_xmsgs\bitgen.xmsgs
AD9512\_xmsgs\map.xmsgs
AD9512\_xmsgs\ngdbuild.xmsgs
AD9512\_xmsgs\par.xmsgs
AD9512\_xmsgs\pn_parser.xmsgs
AD9512\_xmsgs\trce.xmsgs
AD9512\_xmsgs\xst.xmsgs
AD9512\blk_mem_gen_v6_3.mif
AD9512\ipcore_dir
AD9512\ipcore_dir\CSB
AD9512\ipcore_dir\CSB\example_design
AD9512\ipcore_dir\CSB\example_design\CSB_top.ucf
AD9512\ipcore_dir\CSB\example_design\CSB_top.vhd
AD9512\ipcore_dir\CSB\example_design\CSB_top.xdc
AD9512\ipcore_dir\CSB\example_design\bmg_wrapper.vhd
AD9512\ipcore_dir\CSB\implement
AD9512\ipcore_dir\CSB\implement\implement.bat
AD9512\ipcore_dir\CSB\implement\implement.sh
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.bat
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.sh
AD9512\ipcore_dir\CSB\implement\planAhead_rdn.tcl
AD9512\ipcore_dir\CSB\implement\xst.prj
AD9512\ipcore_dir\CSB\implement\xst.scr
AD9512\ipcore_dir\CSB\simulation
AD9512\ipcore_dir\CSB\simulation\addr_gen.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_stim_gen.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_pkg.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_synth.vhd
AD9512\ipcore_dir\CSB\simulation\bmg_tb_top.vhd
AD9512\ipcore_dir\CSB\simulation\functional
AD9512\ipcore_dir\CSB\simulation\functional\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB\simulation\functional\simulate_isim.bat
AD9512\ipcore_dir\CSB\simulation\functional\simulate_mti.do
AD9512\ipcore_dir\CSB\simulation\functional\simulate_ncsim.sh
AD9512\ipcore_dir\CSB\simulation\functional\wave_mti.do
AD9512\ipcore_dir\CSB\simulation\functional\wave_ncsim.sv
AD9512\ipcore_dir\CSB\simulation\random.vhd
AD9512\ipcore_dir\CSB\simulation\timing
AD9512\ipcore_dir\CSB\simulation\timing\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB\simulation\timing\simulate_isim.bat
AD9512\ipcore_dir\CSB\simulation\timing\simulate_mti.do
AD9512\ipcore_dir\CSB\simulation\timing\simulate_ncsim.sh
AD9512\ipcore_dir\CSB\simulation\timing\wave_mti.do
AD9512\ipcore_dir\CSB\simulation\timing\wave_ncsim.sv
AD9512\ipcore_dir\CSB.asy
AD9512\ipcore_dir\CSB.gise
AD9512\ipcore_dir\CSB.mif
AD9512\ipcore_dir\CSB.ngc
AD9512\ipcore_dir\CSB.sym
AD9512\ipcore_dir\CSB.v
AD9512\ipcore_dir\CSB.veo
AD9512\ipcore_dir\CSB.xco
AD9512\ipcore_dir\CSB.xise
AD9512\ipcore_dir\CSB_226
AD9512\ipcore_dir\CSB_226\example_design
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.ucf
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.vhd
AD9512\ipcore_dir\CSB_226\example_design\CSB_226_top.xdc
AD9512\ipcore_dir\CSB_226\example_design\bmg_wrapper.vhd
AD9512\ipcore_dir\CSB_226\implement
AD9512\ipcore_dir\CSB_226\implement\implement.bat
AD9512\ipcore_dir\CSB_226\implement\implement.sh
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.bat
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.sh
AD9512\ipcore_dir\CSB_226\implement\planAhead_rdn.tcl
AD9512\ipcore_dir\CSB_226\implement\xst.prj
AD9512\ipcore_dir\CSB_226\implement\xst.scr
AD9512\ipcore_dir\CSB_226\simulation
AD9512\ipcore_dir\CSB_226\simulation\addr_gen.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_stim_gen.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_pkg.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_synth.vhd
AD9512\ipcore_dir\CSB_226\simulation\bmg_tb_top.vhd
AD9512\ipcore_dir\CSB_226\simulation\functional
AD9512\ipcore_dir\CSB_226\simulation\functional\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_isim.bat
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_mti.do
AD9512\ipcore_dir\CSB_226\simulation\functional\simulate_ncsim.sh
AD9512\ipcore_dir\CSB_226\simulation\functional\wave_mti.do
AD9512\ipcore_dir\CSB_226\simulation\functional\wave_ncsim.sv
AD9512\ipcore_dir\CSB_226\simulation\random.vhd
AD9512\ipcore_dir\CSB_226\simulation\timing
AD9512\ipcore_dir\CSB_226\simulation\timing\isim_tcl_cmds.tcl
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_isim.bat
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_mti.do
AD9512\ipcore_dir\CSB_226\simulation\timing\simulate_ncsim.sh
AD9512\ipcore_dir\CSB_226\simulation\timing\wave_mti.do