文件名称:t2_hpc
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DDR2的控制器设计，完成功能的验证，以及仿真测试，(DDR2 controller design, complete function verification, and simulation test,)
相关搜索： DDR2设计控制器
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下载文件列表
t2_hpc\alt_mem_ddrx_addr_cmd.v
t2_hpc\alt_mem_ddrx_addr_cmd_wrap.v
t2_hpc\alt_mem_ddrx_arbiter.v
t2_hpc\alt_mem_ddrx_buffer.v
t2_hpc\alt_mem_ddrx_buffer_manager.v
t2_hpc\alt_mem_ddrx_burst_gen.v
t2_hpc\alt_mem_ddrx_burst_tracking.v
t2_hpc\alt_mem_ddrx_cmd_gen.v
t2_hpc\alt_mem_ddrx_controller.v
t2_hpc\alt_mem_ddrx_controller_st_top.v
t2_hpc\alt_mem_ddrx_csr.v
t2_hpc\alt_mem_ddrx_dataid_manager.v
t2_hpc\alt_mem_ddrx_ddr2_odt_gen.v
t2_hpc\alt_mem_ddrx_ddr3_odt_gen.v
t2_hpc\alt_mem_ddrx_define.iv
t2_hpc\alt_mem_ddrx_ecc_decoder.v
t2_hpc\alt_mem_ddrx_ecc_decoder_32_syn.v
t2_hpc\alt_mem_ddrx_ecc_decoder_64_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder.v
t2_hpc\alt_mem_ddrx_ecc_encoder_32_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder_64_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
t2_hpc\alt_mem_ddrx_fifo.v
t2_hpc\alt_mem_ddrx_input_if.v
t2_hpc\alt_mem_ddrx_list.v
t2_hpc\alt_mem_ddrx_lpddr2_addr_cmd.v
t2_hpc\alt_mem_ddrx_mm_st_converter.v
t2_hpc\alt_mem_ddrx_odt_gen.v
t2_hpc\alt_mem_ddrx_rank_timer.v
t2_hpc\alt_mem_ddrx_rdata_path.v
t2_hpc\alt_mem_ddrx_rdwr_data_tmg.v
t2_hpc\alt_mem_ddrx_sideband.v
t2_hpc\alt_mem_ddrx_tbp.v
t2_hpc\alt_mem_ddrx_timing_param.v
t2_hpc\alt_mem_ddrx_wdata_path.v
t2_hpc\alt_mem_phy_defines.v
t2_hpc\data_move.bsf
t2_hpc\data_move.v
t2_hpc\data_move.v.bak
t2_hpc\data_move_top.v
t2_hpc\data_move_top.v.bak
t2_hpc\data_move_top_tb.v
t2_hpc\data_move_top_tb.v.bak
t2_hpc\my_ddr.bsf
t2_hpc\my_ddr.html
t2_hpc\my_ddr.ppf
t2_hpc\my_ddr.qip
t2_hpc\my_ddr.v
t2_hpc\my_ddr_advisor.ipa
t2_hpc\my_ddr_alt_mem_ddrx_controller_top.v
t2_hpc\my_ddr_bb.v
t2_hpc\my_ddr_controller_phy.v
t2_hpc\my_ddr_example_driver.v
t2_hpc\my_ddr_example_top.sdc
t2_hpc\my_ddr_example_top.v
t2_hpc\my_ddr_ex_lfsr8.v
t2_hpc\my_ddr_mem_model.v
t2_hpc\my_ddr_phy.bsf
t2_hpc\my_ddr_phy.html
t2_hpc\my_ddr_phy.qip
t2_hpc\my_ddr_phy.v
t2_hpc\my_ddr_phy_alt_mem_phy.v
t2_hpc\my_ddr_phy_alt_mem_phy_pll.mif
t2_hpc\my_ddr_phy_alt_mem_phy_pll.qip
t2_hpc\my_ddr_phy_alt_mem_phy_pll.v
t2_hpc\my_ddr_phy_alt_mem_phy_pll.v_.bak
t2_hpc\my_ddr_phy_alt_mem_phy_pll_bb.v
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig.qip
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig.v
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig_bb.v
t2_hpc\my_ddr_phy_alt_mem_phy_seq.vhd
t2_hpc\my_ddr_phy_alt_mem_phy_seq_wrapper.v
t2_hpc\my_ddr_phy_alt_mem_phy_seq_wrapper.vo
t2_hpc\my_ddr_phy_autodetectedpins.tcl
t2_hpc\my_ddr_phy_bb.v
t2_hpc\my_ddr_phy_ddr_pins.tcl
t2_hpc\my_ddr_phy_ddr_timing.sdc
t2_hpc\my_ddr_phy_report_timing.tcl
t2_hpc\my_ddr_phy_summary.csv
t2_hpc\my_ddr_pin_assignments.tcl
t2_hpc\t2.asm.rpt
t2_hpc\t2.bdf
t2_hpc\t2.done
t2_hpc\t2.eda.rpt
t2_hpc\t2.fit.rpt
t2_hpc\t2.fit.summary
t2_hpc\t2.map.smsg
t2_hpc\t2.map.summary
t2_hpc\t2.pin
t2_hpc\t2.pof
t2_hpc\t2.qpf
t2_hpc\t2.qsf
t2_hpc\t2.sof
t2_hpc\t2.sta.rpt
t2_hpc\t2.sta.summary
t2_hpc\t2.v
t2_hpc\t2_nativelink_simulation.rpt
t2_hpc\t2_tb.v
t2_hpc\t2_tb.v.bak
t2_hpc\testbench\my_ddr_example_top_tb.v
t2_hpc\alt_mem_ddrx_addr_cmd_wrap.v
t2_hpc\alt_mem_ddrx_arbiter.v
t2_hpc\alt_mem_ddrx_buffer.v
t2_hpc\alt_mem_ddrx_buffer_manager.v
t2_hpc\alt_mem_ddrx_burst_gen.v
t2_hpc\alt_mem_ddrx_burst_tracking.v
t2_hpc\alt_mem_ddrx_cmd_gen.v
t2_hpc\alt_mem_ddrx_controller.v
t2_hpc\alt_mem_ddrx_controller_st_top.v
t2_hpc\alt_mem_ddrx_csr.v
t2_hpc\alt_mem_ddrx_dataid_manager.v
t2_hpc\alt_mem_ddrx_ddr2_odt_gen.v
t2_hpc\alt_mem_ddrx_ddr3_odt_gen.v
t2_hpc\alt_mem_ddrx_define.iv
t2_hpc\alt_mem_ddrx_ecc_decoder.v
t2_hpc\alt_mem_ddrx_ecc_decoder_32_syn.v
t2_hpc\alt_mem_ddrx_ecc_decoder_64_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder.v
t2_hpc\alt_mem_ddrx_ecc_encoder_32_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder_64_syn.v
t2_hpc\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
t2_hpc\alt_mem_ddrx_fifo.v
t2_hpc\alt_mem_ddrx_input_if.v
t2_hpc\alt_mem_ddrx_list.v
t2_hpc\alt_mem_ddrx_lpddr2_addr_cmd.v
t2_hpc\alt_mem_ddrx_mm_st_converter.v
t2_hpc\alt_mem_ddrx_odt_gen.v
t2_hpc\alt_mem_ddrx_rank_timer.v
t2_hpc\alt_mem_ddrx_rdata_path.v
t2_hpc\alt_mem_ddrx_rdwr_data_tmg.v
t2_hpc\alt_mem_ddrx_sideband.v
t2_hpc\alt_mem_ddrx_tbp.v
t2_hpc\alt_mem_ddrx_timing_param.v
t2_hpc\alt_mem_ddrx_wdata_path.v
t2_hpc\alt_mem_phy_defines.v
t2_hpc\data_move.bsf
t2_hpc\data_move.v
t2_hpc\data_move.v.bak
t2_hpc\data_move_top.v
t2_hpc\data_move_top.v.bak
t2_hpc\data_move_top_tb.v
t2_hpc\data_move_top_tb.v.bak
t2_hpc\my_ddr.bsf
t2_hpc\my_ddr.html
t2_hpc\my_ddr.ppf
t2_hpc\my_ddr.qip
t2_hpc\my_ddr.v
t2_hpc\my_ddr_advisor.ipa
t2_hpc\my_ddr_alt_mem_ddrx_controller_top.v
t2_hpc\my_ddr_bb.v
t2_hpc\my_ddr_controller_phy.v
t2_hpc\my_ddr_example_driver.v
t2_hpc\my_ddr_example_top.sdc
t2_hpc\my_ddr_example_top.v
t2_hpc\my_ddr_ex_lfsr8.v
t2_hpc\my_ddr_mem_model.v
t2_hpc\my_ddr_phy.bsf
t2_hpc\my_ddr_phy.html
t2_hpc\my_ddr_phy.qip
t2_hpc\my_ddr_phy.v
t2_hpc\my_ddr_phy_alt_mem_phy.v
t2_hpc\my_ddr_phy_alt_mem_phy_pll.mif
t2_hpc\my_ddr_phy_alt_mem_phy_pll.qip
t2_hpc\my_ddr_phy_alt_mem_phy_pll.v
t2_hpc\my_ddr_phy_alt_mem_phy_pll.v_.bak
t2_hpc\my_ddr_phy_alt_mem_phy_pll_bb.v
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig.qip
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig.v
t2_hpc\my_ddr_phy_alt_mem_phy_reconfig_bb.v
t2_hpc\my_ddr_phy_alt_mem_phy_seq.vhd
t2_hpc\my_ddr_phy_alt_mem_phy_seq_wrapper.v
t2_hpc\my_ddr_phy_alt_mem_phy_seq_wrapper.vo
t2_hpc\my_ddr_phy_autodetectedpins.tcl
t2_hpc\my_ddr_phy_bb.v
t2_hpc\my_ddr_phy_ddr_pins.tcl
t2_hpc\my_ddr_phy_ddr_timing.sdc
t2_hpc\my_ddr_phy_report_timing.tcl
t2_hpc\my_ddr_phy_summary.csv
t2_hpc\my_ddr_pin_assignments.tcl
t2_hpc\t2.asm.rpt
t2_hpc\t2.bdf
t2_hpc\t2.done
t2_hpc\t2.eda.rpt
t2_hpc\t2.fit.rpt
t2_hpc\t2.fit.summary
t2_hpc\t2.map.smsg
t2_hpc\t2.map.summary
t2_hpc\t2.pin
t2_hpc\t2.pof
t2_hpc\t2.qpf
t2_hpc\t2.qsf
t2_hpc\t2.sof
t2_hpc\t2.sta.rpt
t2_hpc\t2.sta.summary
t2_hpc\t2.v
t2_hpc\t2_nativelink_simulation.rpt
t2_hpc\t2_tb.v
t2_hpc\t2_tb.v.bak
t2_hpc\testbench\my_ddr_example_top_tb.v