文件名称:design-IR-Verilog
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IR传感器使用Verilog语言编程，平台实在FPGA Cycle 4上实现(IR sensor using Verilog programming language, the platform is really FPGA Cycle 4 implementation)
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下载文件列表
design-IR-Verilog\beep.v
design-IR-Verilog\db\altsyncram_2r14.tdf
design-IR-Verilog\db\altsyncram_4r14.tdf
design-IR-Verilog\db\beep.map_bb.logdb
design-IR-Verilog\db\beep.smp_dump.txt
design-IR-Verilog\db\cmpr_ngc.tdf
design-IR-Verilog\db\cmpr_qgc.tdf
design-IR-Verilog\db\cntr_23j.tdf
design-IR-Verilog\db\cntr_egi.tdf
design-IR-Verilog\db\cntr_i6j.tdf
design-IR-Verilog\db\decode_dvf.tdf
design-IR-Verilog\db\dt.map_bb.logdb
design-IR-Verilog\db\dt.smp_dump.txt
design-IR-Verilog\db\IR.map_bb.logdb
design-IR-Verilog\db\IR.smp_dump.txt
design-IR-Verilog\db\key.map_bb.logdb
design-IR-Verilog\db\key.smp_dump.txt
design-IR-Verilog\db\led.map_bb.logdb
design-IR-Verilog\db\led.smp_dump.txt
design-IR-Verilog\db\logic_util_heursitic.dat
design-IR-Verilog\db\mux_ssc.tdf
design-IR-Verilog\db\prev_cmp_beep.qmsg
design-IR-Verilog\db\prev_cmp_dt.qmsg
design-IR-Verilog\db\prev_cmp_IR.qmsg
design-IR-Verilog\db\prev_cmp_key.qmsg
design-IR-Verilog\db\prev_cmp_led.qmsg
design-IR-Verilog\db\top.ae.hdb
design-IR-Verilog\db\top.amm.cdb
design-IR-Verilog\db\top.asm.qmsg
design-IR-Verilog\db\top.asm.rdb
design-IR-Verilog\db\top.asm_labs.ddb
design-IR-Verilog\db\top.atom.rvd
design-IR-Verilog\db\top.autoh_e4eb1.map.reg_db.cdb
design-IR-Verilog\db\top.autos_3e921.map.reg_db.cdb
design-IR-Verilog\db\top.cbx.xml
design-IR-Verilog\db\top.cmp.bpm
design-IR-Verilog\db\top.cmp.cdb
design-IR-Verilog\db\top.cmp.hdb
design-IR-Verilog\db\top.cmp.kpt
design-IR-Verilog\db\top.cmp.logdb
design-IR-Verilog\db\top.cmp.rdb
design-IR-Verilog\db\top.cmp_merge.kpt
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
design-IR-Verilog\db\top.db_info
design-IR-Verilog\db\top.eda.qmsg
design-IR-Verilog\db\top.fit.qmsg
design-IR-Verilog\db\top.hier_info
design-IR-Verilog\db\top.hif
design-IR-Verilog\db\top.idb.cdb
design-IR-Verilog\db\top.lfp.cdb
design-IR-Verilog\db\top.lpc.html
design-IR-Verilog\db\top.lpc.rdb
design-IR-Verilog\db\top.lpc.txt
design-IR-Verilog\db\top.map.bpm
design-IR-Verilog\db\top.map.cdb
design-IR-Verilog\db\top.map.hdb
design-IR-Verilog\db\top.map.kpt
design-IR-Verilog\db\top.map.qmsg
design-IR-Verilog\db\top.map_bb.cdb
design-IR-Verilog\db\top.map_bb.hdb
design-IR-Verilog\db\top.pre_map.cdb
design-IR-Verilog\db\top.pre_map.hdb
design-IR-Verilog\db\top.root_partition.map.reg_db.cdb
design-IR-Verilog\db\top.rpp.qmsg
design-IR-Verilog\db\top.rtlv.hdb
design-IR-Verilog\db\top.rtlv_sg.cdb
design-IR-Verilog\db\top.rtlv_sg_swap.cdb
design-IR-Verilog\db\top.sgate.rvd
design-IR-Verilog\db\top.sgate_sm.rvd
design-IR-Verilog\db\top.sgdiff.cdb
design-IR-Verilog\db\top.sgdiff.hdb
design-IR-Verilog\db\top.sld_design_entry.sci
design-IR-Verilog\db\top.sld_design_entry_dsc.sci
design-IR-Verilog\db\top.smart_action.txt
design-IR-Verilog\db\top.sta.qmsg
design-IR-Verilog\db\top.sta.rdb
design-IR-Verilog\db\top.sta_cmp.8_slow_1200mv_85c.tdb
design-IR-Verilog\db\top.syn_hier_info
design-IR-Verilog\db\top.tiscmp.fastest_slow_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.fastest_slow_1200mv_85c.ddb
design-IR-Verilog\db\top.tiscmp.fast_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.slow_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.slow_1200mv_85c.ddb
design-IR-Verilog\db\top.tis_db_list.ddb
design-IR-Verilog\dt.v
design-IR-Verilog\greybox_tmp\cbx_args.txt
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.cdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.dpi
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.hdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.kpt
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.logdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.cdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.dpi
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.hdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.kpt
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.logdb
design-IR-Verilog\incremental_db\compiled_partitions\top.db_info
design-IR-Verilog\incremental_db\compiled_partitions\top.root_partition.cmp.cdb
design-IR-Verilog\db\altsyncram_2r14.tdf
design-IR-Verilog\db\altsyncram_4r14.tdf
design-IR-Verilog\db\beep.map_bb.logdb
design-IR-Verilog\db\beep.smp_dump.txt
design-IR-Verilog\db\cmpr_ngc.tdf
design-IR-Verilog\db\cmpr_qgc.tdf
design-IR-Verilog\db\cntr_23j.tdf
design-IR-Verilog\db\cntr_egi.tdf
design-IR-Verilog\db\cntr_i6j.tdf
design-IR-Verilog\db\decode_dvf.tdf
design-IR-Verilog\db\dt.map_bb.logdb
design-IR-Verilog\db\dt.smp_dump.txt
design-IR-Verilog\db\IR.map_bb.logdb
design-IR-Verilog\db\IR.smp_dump.txt
design-IR-Verilog\db\key.map_bb.logdb
design-IR-Verilog\db\key.smp_dump.txt
design-IR-Verilog\db\led.map_bb.logdb
design-IR-Verilog\db\led.smp_dump.txt
design-IR-Verilog\db\logic_util_heursitic.dat
design-IR-Verilog\db\mux_ssc.tdf
design-IR-Verilog\db\prev_cmp_beep.qmsg
design-IR-Verilog\db\prev_cmp_dt.qmsg
design-IR-Verilog\db\prev_cmp_IR.qmsg
design-IR-Verilog\db\prev_cmp_key.qmsg
design-IR-Verilog\db\prev_cmp_led.qmsg
design-IR-Verilog\db\top.ae.hdb
design-IR-Verilog\db\top.amm.cdb
design-IR-Verilog\db\top.asm.qmsg
design-IR-Verilog\db\top.asm.rdb
design-IR-Verilog\db\top.asm_labs.ddb
design-IR-Verilog\db\top.atom.rvd
design-IR-Verilog\db\top.autoh_e4eb1.map.reg_db.cdb
design-IR-Verilog\db\top.autos_3e921.map.reg_db.cdb
design-IR-Verilog\db\top.cbx.xml
design-IR-Verilog\db\top.cmp.bpm
design-IR-Verilog\db\top.cmp.cdb
design-IR-Verilog\db\top.cmp.hdb
design-IR-Verilog\db\top.cmp.kpt
design-IR-Verilog\db\top.cmp.logdb
design-IR-Verilog\db\top.cmp.rdb
design-IR-Verilog\db\top.cmp_merge.kpt
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
design-IR-Verilog\db\top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
design-IR-Verilog\db\top.db_info
design-IR-Verilog\db\top.eda.qmsg
design-IR-Verilog\db\top.fit.qmsg
design-IR-Verilog\db\top.hier_info
design-IR-Verilog\db\top.hif
design-IR-Verilog\db\top.idb.cdb
design-IR-Verilog\db\top.lfp.cdb
design-IR-Verilog\db\top.lpc.html
design-IR-Verilog\db\top.lpc.rdb
design-IR-Verilog\db\top.lpc.txt
design-IR-Verilog\db\top.map.bpm
design-IR-Verilog\db\top.map.cdb
design-IR-Verilog\db\top.map.hdb
design-IR-Verilog\db\top.map.kpt
design-IR-Verilog\db\top.map.qmsg
design-IR-Verilog\db\top.map_bb.cdb
design-IR-Verilog\db\top.map_bb.hdb
design-IR-Verilog\db\top.pre_map.cdb
design-IR-Verilog\db\top.pre_map.hdb
design-IR-Verilog\db\top.root_partition.map.reg_db.cdb
design-IR-Verilog\db\top.rpp.qmsg
design-IR-Verilog\db\top.rtlv.hdb
design-IR-Verilog\db\top.rtlv_sg.cdb
design-IR-Verilog\db\top.rtlv_sg_swap.cdb
design-IR-Verilog\db\top.sgate.rvd
design-IR-Verilog\db\top.sgate_sm.rvd
design-IR-Verilog\db\top.sgdiff.cdb
design-IR-Verilog\db\top.sgdiff.hdb
design-IR-Verilog\db\top.sld_design_entry.sci
design-IR-Verilog\db\top.sld_design_entry_dsc.sci
design-IR-Verilog\db\top.smart_action.txt
design-IR-Verilog\db\top.sta.qmsg
design-IR-Verilog\db\top.sta.rdb
design-IR-Verilog\db\top.sta_cmp.8_slow_1200mv_85c.tdb
design-IR-Verilog\db\top.syn_hier_info
design-IR-Verilog\db\top.tiscmp.fastest_slow_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.fastest_slow_1200mv_85c.ddb
design-IR-Verilog\db\top.tiscmp.fast_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.slow_1200mv_0c.ddb
design-IR-Verilog\db\top.tiscmp.slow_1200mv_85c.ddb
design-IR-Verilog\db\top.tis_db_list.ddb
design-IR-Verilog\dt.v
design-IR-Verilog\greybox_tmp\cbx_args.txt
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.cdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.dpi
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.hdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.kpt
design-IR-Verilog\incremental_db\compiled_partitions\top.autoh_e4eb1.map.logdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.cdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.dpi
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.hdb
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.kpt
design-IR-Verilog\incremental_db\compiled_partitions\top.autos_3e921.map.logdb
design-IR-Verilog\incremental_db\compiled_partitions\top.db_info
design-IR-Verilog\incremental_db\compiled_partitions\top.root_partition.cmp.cdb