文件名称:RS_422
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2017-07-07
- 文件大小：
- 5.61mb
- 下载次数：
- 0次
- 提 供 者：
- allen*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
在K7FPGA上利用verilog语言编写的RS422串口，由于没找到Verilog所以选择了VHDL(On the K7FPGA, using Verilog language RS422 serial port, because did not find Verilog, so chose VHDL)
相关搜索： rs422
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下载文件列表
RS_422
RS_422\.Xil
RS_422\.lso
RS_422\RS_422.gise
RS_422\RS_422.xise
RS_422\SETDATAuart_send.cmd_log
RS_422\SETDATAuart_send.tfi
RS_422\SETDATAuart_send.v
RS_422\SETDATAuart_send_isim_beh.exe
RS_422\SETDATAuart_send_stx_beh.prj
RS_422\_ngo
RS_422\_ngo\netlist.lst
RS_422\_xmsgs
RS_422\_xmsgs\bitgen.xmsgs
RS_422\_xmsgs\map.xmsgs
RS_422\_xmsgs\ngdbuild.xmsgs
RS_422\_xmsgs\par.xmsgs
RS_422\_xmsgs\pn_parser.xmsgs
RS_422\_xmsgs\trce.xmsgs
RS_422\_xmsgs\xst.xmsgs
RS_422\control_ram.cmd_log
RS_422\control_ram.tfi
RS_422\control_ram.v
RS_422\div_1_8m.cmd_log
RS_422\div_1_8m.prj
RS_422\div_1_8m.spl
RS_422\div_1_8m.stx
RS_422\div_1_8m.sym
RS_422\div_1_8m.tfi
RS_422\div_1_8m.v
RS_422\div_1_8m.xst
RS_422\div_baud.cmd_log
RS_422\div_baud.spl
RS_422\div_baud.sym
RS_422\div_baud.tfi
RS_422\div_baud.v
RS_422\fuse.log
RS_422\fuse.xmsgs
RS_422\fuseRelaunch.cmd
RS_422\ipcore_dir
RS_422\ipcore_dir\RAM
RS_422\ipcore_dir\RAM\blk_mem_gen_v7_3_readme.txt
RS_422\ipcore_dir\RAM\doc
RS_422\ipcore_dir\RAM\doc\blk_mem_gen_v7_3_vinfo.html
RS_422\ipcore_dir\RAM\doc\pg058-blk-mem-gen.pdf
RS_422\ipcore_dir\RAM\example_design
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.ucf
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.vhd
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.xdc
RS_422\ipcore_dir\RAM\example_design\RAM_prod.vhd
RS_422\ipcore_dir\RAM\implement
RS_422\ipcore_dir\RAM\implement\implement.bat
RS_422\ipcore_dir\RAM\implement\implement.sh
RS_422\ipcore_dir\RAM\implement\planAhead_ise.bat
RS_422\ipcore_dir\RAM\implement\planAhead_ise.sh
RS_422\ipcore_dir\RAM\implement\planAhead_ise.tcl
RS_422\ipcore_dir\RAM\implement\xst.prj
RS_422\ipcore_dir\RAM\implement\xst.scr
RS_422\ipcore_dir\RAM\simulation
RS_422\ipcore_dir\RAM\simulation\RAM_synth.vhd
RS_422\ipcore_dir\RAM\simulation\RAM_tb.vhd
RS_422\ipcore_dir\RAM\simulation\addr_gen.vhd
RS_422\ipcore_dir\RAM\simulation\bmg_stim_gen.vhd
RS_422\ipcore_dir\RAM\simulation\bmg_tb_pkg.vhd
RS_422\ipcore_dir\RAM\simulation\checker.vhd
RS_422\ipcore_dir\RAM\simulation\data_gen.vhd
RS_422\ipcore_dir\RAM\simulation\functional
RS_422\ipcore_dir\RAM\simulation\functional\simcmds.tcl
RS_422\ipcore_dir\RAM\simulation\functional\simulate_isim.bat
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.bat
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.do
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.sh
RS_422\ipcore_dir\RAM\simulation\functional\simulate_ncsim.sh
RS_422\ipcore_dir\RAM\simulation\functional\simulate_vcs.sh
RS_422\ipcore_dir\RAM\simulation\functional\ucli_commands.key
RS_422\ipcore_dir\RAM\simulation\functional\vcs_session.tcl
RS_422\ipcore_dir\RAM\simulation\functional\wave_mti.do
RS_422\ipcore_dir\RAM\simulation\functional\wave_ncsim.sv
RS_422\ipcore_dir\RAM\simulation\random.vhd
RS_422\ipcore_dir\RAM\simulation\timing
RS_422\ipcore_dir\RAM\simulation\timing\simcmds.tcl
RS_422\ipcore_dir\RAM\simulation\timing\simulate_isim.bat
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.bat
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.do
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.sh
RS_422\ipcore_dir\RAM\simulation\timing\simulate_ncsim.sh
RS_422\ipcore_dir\RAM\simulation\timing\simulate_vcs.sh
RS_422\ipcore_dir\RAM\simulation\timing\ucli_commands.key
RS_422\ipcore_dir\RAM\simulation\timing\vcs_session.tcl
RS_422\ipcore_dir\RAM\simulation\timing\wave_mti.do
RS_422\ipcore_dir\RAM\simulation\timing\wave_ncsim.sv
RS_422\ipcore_dir\RAM.asy
RS_422\ipcore_dir\RAM.gise
RS_422\ipcore_dir\RAM.ncf
RS_422\ipcore_dir\RAM.ngc
RS_422\ipcore_dir\RAM.sym
RS_422\ipcore_dir\RAM.v
RS_422\ipcore_dir\RAM.veo
RS_422\ipcore_dir\RAM.xco
RS_422\ipcore_dir\RAM.xise
RS_422\.Xil
RS_422\.lso
RS_422\RS_422.gise
RS_422\RS_422.xise
RS_422\SETDATAuart_send.cmd_log
RS_422\SETDATAuart_send.tfi
RS_422\SETDATAuart_send.v
RS_422\SETDATAuart_send_isim_beh.exe
RS_422\SETDATAuart_send_stx_beh.prj
RS_422\_ngo
RS_422\_ngo\netlist.lst
RS_422\_xmsgs
RS_422\_xmsgs\bitgen.xmsgs
RS_422\_xmsgs\map.xmsgs
RS_422\_xmsgs\ngdbuild.xmsgs
RS_422\_xmsgs\par.xmsgs
RS_422\_xmsgs\pn_parser.xmsgs
RS_422\_xmsgs\trce.xmsgs
RS_422\_xmsgs\xst.xmsgs
RS_422\control_ram.cmd_log
RS_422\control_ram.tfi
RS_422\control_ram.v
RS_422\div_1_8m.cmd_log
RS_422\div_1_8m.prj
RS_422\div_1_8m.spl
RS_422\div_1_8m.stx
RS_422\div_1_8m.sym
RS_422\div_1_8m.tfi
RS_422\div_1_8m.v
RS_422\div_1_8m.xst
RS_422\div_baud.cmd_log
RS_422\div_baud.spl
RS_422\div_baud.sym
RS_422\div_baud.tfi
RS_422\div_baud.v
RS_422\fuse.log
RS_422\fuse.xmsgs
RS_422\fuseRelaunch.cmd
RS_422\ipcore_dir
RS_422\ipcore_dir\RAM
RS_422\ipcore_dir\RAM\blk_mem_gen_v7_3_readme.txt
RS_422\ipcore_dir\RAM\doc
RS_422\ipcore_dir\RAM\doc\blk_mem_gen_v7_3_vinfo.html
RS_422\ipcore_dir\RAM\doc\pg058-blk-mem-gen.pdf
RS_422\ipcore_dir\RAM\example_design
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.ucf
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.vhd
RS_422\ipcore_dir\RAM\example_design\RAM_exdes.xdc
RS_422\ipcore_dir\RAM\example_design\RAM_prod.vhd
RS_422\ipcore_dir\RAM\implement
RS_422\ipcore_dir\RAM\implement\implement.bat
RS_422\ipcore_dir\RAM\implement\implement.sh
RS_422\ipcore_dir\RAM\implement\planAhead_ise.bat
RS_422\ipcore_dir\RAM\implement\planAhead_ise.sh
RS_422\ipcore_dir\RAM\implement\planAhead_ise.tcl
RS_422\ipcore_dir\RAM\implement\xst.prj
RS_422\ipcore_dir\RAM\implement\xst.scr
RS_422\ipcore_dir\RAM\simulation
RS_422\ipcore_dir\RAM\simulation\RAM_synth.vhd
RS_422\ipcore_dir\RAM\simulation\RAM_tb.vhd
RS_422\ipcore_dir\RAM\simulation\addr_gen.vhd
RS_422\ipcore_dir\RAM\simulation\bmg_stim_gen.vhd
RS_422\ipcore_dir\RAM\simulation\bmg_tb_pkg.vhd
RS_422\ipcore_dir\RAM\simulation\checker.vhd
RS_422\ipcore_dir\RAM\simulation\data_gen.vhd
RS_422\ipcore_dir\RAM\simulation\functional
RS_422\ipcore_dir\RAM\simulation\functional\simcmds.tcl
RS_422\ipcore_dir\RAM\simulation\functional\simulate_isim.bat
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.bat
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.do
RS_422\ipcore_dir\RAM\simulation\functional\simulate_mti.sh
RS_422\ipcore_dir\RAM\simulation\functional\simulate_ncsim.sh
RS_422\ipcore_dir\RAM\simulation\functional\simulate_vcs.sh
RS_422\ipcore_dir\RAM\simulation\functional\ucli_commands.key
RS_422\ipcore_dir\RAM\simulation\functional\vcs_session.tcl
RS_422\ipcore_dir\RAM\simulation\functional\wave_mti.do
RS_422\ipcore_dir\RAM\simulation\functional\wave_ncsim.sv
RS_422\ipcore_dir\RAM\simulation\random.vhd
RS_422\ipcore_dir\RAM\simulation\timing
RS_422\ipcore_dir\RAM\simulation\timing\simcmds.tcl
RS_422\ipcore_dir\RAM\simulation\timing\simulate_isim.bat
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.bat
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.do
RS_422\ipcore_dir\RAM\simulation\timing\simulate_mti.sh
RS_422\ipcore_dir\RAM\simulation\timing\simulate_ncsim.sh
RS_422\ipcore_dir\RAM\simulation\timing\simulate_vcs.sh
RS_422\ipcore_dir\RAM\simulation\timing\ucli_commands.key
RS_422\ipcore_dir\RAM\simulation\timing\vcs_session.tcl
RS_422\ipcore_dir\RAM\simulation\timing\wave_mti.do
RS_422\ipcore_dir\RAM\simulation\timing\wave_ncsim.sv
RS_422\ipcore_dir\RAM.asy
RS_422\ipcore_dir\RAM.gise
RS_422\ipcore_dir\RAM.ncf
RS_422\ipcore_dir\RAM.ngc
RS_422\ipcore_dir\RAM.sym
RS_422\ipcore_dir\RAM.v
RS_422\ipcore_dir\RAM.veo
RS_422\ipcore_dir\RAM.xco
RS_422\ipcore_dir\RAM.xise