文件名称:pll_self_rst

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2017-07-07
  • 文件大小:
  • 471kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • njit****
  • 相关连接:
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用于检测ALTERA FPGA PLL应用中出现的假锁定问题(Used to detect false lock problems in ALTERA FPGA
PLL applications)
相关搜索: fpga
pll

(系统自动生成,下载前可以参看下载内容)

下载文件列表

pll_self_rst\lib\pll_125m.v

pll_self_rst\sim\220model.v

pll_self_rst\sim\altera_mf.v

pll_self_rst\sim\altera_primitives.v

pll_self_rst\sim\clk_det.v

pll_self_rst\sim\modelsim.ini

pll_self_rst\sim\pll_125m.v

pll_self_rst\sim\pll_rst_ctrl.v

pll_self_rst\sim\run.bat

pll_self_rst\sim\run.tcl

pll_self_rst\sim\sgate.v

pll_self_rst\sim\tb.v

pll_self_rst\sim\transcript

pll_self_rst\sim\vsim.txt

pll_self_rst\sim\vsim.wlf

pll_self_rst\sim\wave.do

pll_self_rst\src\pll_rst_ctrl.v

pll_self_rst\syn\pll_rst_ctrl.prd

pll_self_rst\syn\pll_rst_ctrl.prj

pll_self_rst\syn\rev_1\AutoConstraint_pll_rst_ctrl.sdc

pll_self_rst\syn\rev_1\backup\pll_rst_ctrl.srr

pll_self_rst\syn\rev_1\dm\layer0.xdm

pll_self_rst\syn\rev_1\fvpr_characteristics.txt

pll_self_rst\syn\rev_1\pll_rst_ctrl.edf

pll_self_rst\syn\rev_1\pll_rst_ctrl.fse

pll_self_rst\syn\rev_1\pll_rst_ctrl.htm

pll_self_rst\syn\rev_1\pll_rst_ctrl.map

pll_self_rst\syn\rev_1\pll_rst_ctrl.ncf

pll_self_rst\syn\rev_1\pll_rst_ctrl.sap

pll_self_rst\syn\rev_1\pll_rst_ctrl.scf

pll_self_rst\syn\rev_1\pll_rst_ctrl.srd

pll_self_rst\syn\rev_1\pll_rst_ctrl.srm

pll_self_rst\syn\rev_1\pll_rst_ctrl.srr

pll_self_rst\syn\rev_1\pll_rst_ctrl.srs

pll_self_rst\syn\rev_1\pll_rst_ctrl.sxr

pll_self_rst\syn\rev_1\pll_rst_ctrl.szr

pll_self_rst\syn\rev_1\pll_rst_ctrl.tcl

pll_self_rst\syn\rev_1\pll_rst_ctrl.tlg

pll_self_rst\syn\rev_1\pll_rst_ctrl.vqm

pll_self_rst\syn\rev_1\pll_rst_ctrl_cons.tcl

pll_self_rst\syn\rev_1\pll_rst_ctrl_dsp.fdc

pll_self_rst\syn\rev_1\pll_rst_ctrl_rm.tcl

pll_self_rst\syn\rev_1\pll_rst_ctrl_scck.rpt

pll_self_rst\syn\rev_1\pll_rst_ctrl_synplify.fdc

pll_self_rst\syn\rev_1\rpt_pll_rst_ctrl.areasrr

pll_self_rst\syn\rev_1\rpt_pll_rst_ctrl_areasrr.htm

pll_self_rst\syn\rev_1\run_ise.tcl

pll_self_rst\syn\rev_1\run_options.txt

pll_self_rst\syn\rev_1\scratchproject.prs

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_compiler.srr

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_compiler.srr.rptmap

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_fpga_mapper.srr

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_fpga_mapper.srr_Min

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_fpga_mapper.szr

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_fpga_mapper.xck

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_multi_srs_gen.srr

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_premap.srr

pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_premap.szr

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_compiler_notes.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_compiler_runstatus.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_area_report.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_combined_clk.rpt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_errors.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_notes.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_opt_report.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_resourceusage.rpt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_runstatus.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_timing_report.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_warnings.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_premap_errors.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_premap_notes.txt

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_premap_runstatus.xml

pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_premap_warnings.txt

pll_self_rst\syn\rev_1\synlog\syntax_constraint_check.rpt.rptmap

pll_self_rst\syn\rev_1\synplicity.ucf

pll_self_rst\syn\rev_1\syntmp\clearbox_param

pll_self_rst\syn\rev_1\syntmp\clearbox_version.v

pll_self_rst\syn\rev_1\syntmp\closed.png

pll_self_rst\syn\rev_1\syntmp\cmdrec_compiler.log

pll_self_rst\syn\rev_1\syntmp\cmdrec_fpga_mapper.log

pll_self_rst\syn\rev_1\syntmp\cmdrec_multi_srs_gen.log

pll_self_rst\syn\rev_1\syntmp\cmdrec_premap.log

pll_self_rst\syn\rev_1\syntmp\open.png

pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl.plg

pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_cons_ui.tcl

pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_flink.htm

pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_srr.htm

pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_toc.htm

pll_self_rst\syn\rev_1\syntmp\run_option.xml

pll_self_rst\syn\rev_1\syntmp\sap.log

pll_self_rst\syn\rev_1\syntmp\statusReport.html

pll_self_rst\syn\rev_1\synwork\.cckTransfer

pll_self_rst\syn\rev_1\synwork\layer0.fdep

pll_self_rst\syn\rev_1\synwork\layer0.fdepxmr

pll_self_rst\syn\rev_1\synwork\layer0.srs

pll_self_rst\syn\rev_1\synwork\layer0.tlg

pll_self_rst\syn\rev_1\synwork\pll_rst_ctrl_comp.fdep

pll_self_rst\syn\rev_1\synwork\pll_rst_ctrl_comp.srs

pll_self_rst\syn\rev_1\synwork\pll_rst_ctrl_m.srm

pll_self_rst\syn\rev_1\synwork\pll_rst_ctrl_mult.srs

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