DE2_Basic_Computer\app_software

DE2_Basic_Computer\app_software\complete_test_C

DE2_Basic_Computer\app_software\complete_test_C\address_map.h

DE2_Basic_Computer\app_software\complete_test_C\complete_test.c

DE2_Basic_Computer\app_software\complete_test_C\complete_test_C_verilog.ncf

DE2_Basic_Computer\app_software\complete_test_C\complete_test_C_vhdl.ncf

DE2_Basic_Computer\app_software\complete_test_C\exceptions.c

DE2_Basic_Computer\app_software\complete_test_C\interval_timer.c

DE2_Basic_Computer\app_software\complete_test_C\nios2_ctrl_reg_macros.h

DE2_Basic_Computer\app_software\complete_test_C\pushbutton.c

DE2_Basic_Computer\app_software\complete_test_s

DE2_Basic_Computer\app_software\complete_test_s\address_map.s

DE2_Basic_Computer\app_software\complete_test_s\complete_test.s

DE2_Basic_Computer\app_software\complete_test_s\complete_test_s_verilog.ncf

DE2_Basic_Computer\app_software\complete_test_s\complete_test_s_vhdl.ncf

DE2_Basic_Computer\app_software\complete_test_s\exceptions.s

DE2_Basic_Computer\app_software\complete_test_s\interval_timer.s

DE2_Basic_Computer\app_software\complete_test_s\pushbutton.s

DE2_Basic_Computer\app_software\example_code_C

DE2_Basic_Computer\app_software\example_code_C\address_map.h

DE2_Basic_Computer\app_software\example_code_C\example_code.c

DE2_Basic_Computer\app_software\example_code_C\example_code_C_verilog.ncf

DE2_Basic_Computer\app_software\example_code_C\example_code_C_vhdl.ncf

DE2_Basic_Computer\app_software\example_code_C\exceptions.c

DE2_Basic_Computer\app_software\example_code_C\nios2_ctrl_reg_macros.h

DE2_Basic_Computer\app_software\example_code_C\pushbutton.c

DE2_Basic_Computer\app_software\example_code_s

DE2_Basic_Computer\app_software\example_code_s\address_map.s

DE2_Basic_Computer\app_software\example_code_s\example_code.s

DE2_Basic_Computer\app_software\example_code_s\example_code_s_verilog.ncf

DE2_Basic_Computer\app_software\example_code_s\example_code_s_vhdl.ncf

DE2_Basic_Computer\app_software\example_code_s\exceptions.s

DE2_Basic_Computer\app_software\example_code_s\pushbutton.s

DE2_Basic_Computer\doc

DE2_Basic_Computer\doc\DE2_Basic_Computer.pdf

DE2_Basic_Computer\doc\DE2_Basic_Computer.tex

DE2_Basic_Computer\doc\fig_block_diagram.fm

DE2_Basic_Computer\doc\fig_block_diagram.pdf

DE2_Basic_Computer\doc\fig_expansion_port.fm

DE2_Basic_Computer\doc\fig_expansion_port.pdf

DE2_Basic_Computer\doc\fig_interval_port.fm

DE2_Basic_Computer\doc\fig_interval_port.pdf

DE2_Basic_Computer\doc\fig_jtag_port.fm

DE2_Basic_Computer\doc\fig_jtag_port.pdf

DE2_Basic_Computer\doc\fig_LED_port.fm

DE2_Basic_Computer\doc\fig_LED_port.pdf

DE2_Basic_Computer\doc\fig_parallel_port.fm

DE2_Basic_Computer\doc\fig_parallel_port.pdf

DE2_Basic_Computer\doc\fig_pushbutton_port.fm

DE2_Basic_Computer\doc\fig_pushbutton_port.pdf

DE2_Basic_Computer\doc\fig_segment_port.fm

DE2_Basic_Computer\doc\fig_segment_port.pdf

DE2_Basic_Computer\doc\fig_serial_port.fm

DE2_Basic_Computer\doc\fig_serial_port.pdf

DE2_Basic_Computer\doc\fig_slider_port.fm

DE2_Basic_Computer\doc\fig_slider_port.pdf

DE2_Basic_Computer\verilog

DE2_Basic_Computer\verilog\Altera_UP_Hexadecimal_To_Seven_Segment.v

DE2_Basic_Computer\verilog\Altera_UP_RS232_Counters.v

DE2_Basic_Computer\verilog\Altera_UP_RS232_In_Deserializer.v

DE2_Basic_Computer\verilog\Altera_UP_RS232_Out_Serializer.v

DE2_Basic_Computer\verilog\Altera_UP_SYNC_FIFO.v

DE2_Basic_Computer\verilog\cpu.v

DE2_Basic_Computer\verilog\cpu_ic_tag_ram.mif

DE2_Basic_Computer\verilog\cpu_jtag_debug_module.v

DE2_Basic_Computer\verilog\cpu_jtag_debug_module_wrapper.v

DE2_Basic_Computer\verilog\cpu_mult_cell.v

DE2_Basic_Computer\verilog\cpu_ociram_default_contents.mif

DE2_Basic_Computer\verilog\cpu_rf_ram.mif

DE2_Basic_Computer\verilog\cpu_rf_ram_a.mif

DE2_Basic_Computer\verilog\cpu_rf_ram_b.mif

DE2_Basic_Computer\verilog\cpu_test_bench.v

DE2_Basic_Computer\verilog\DE2_Basic_Computer.pof

DE2_Basic_Computer\verilog\DE2_Basic_Computer.qpf

DE2_Basic_Computer\verilog\DE2_Basic_Computer.qsf

DE2_Basic_Computer\verilog\DE2_Basic_Computer.sof

DE2_Basic_Computer\verilog\DE2_Basic_Computer.v

DE2_Basic_Computer\verilog\Expansion_JP1.v

DE2_Basic_Computer\verilog\Expansion_JP2.v

DE2_Basic_Computer\verilog\Green_LEDs.v

DE2_Basic_Computer\verilog\HEX3_HEX0.v

DE2_Basic_Computer\verilog\HEX7_HEX4.v

DE2_Basic_Computer\verilog\Interval_timer.v

DE2_Basic_Computer\verilog\jtag_uart.v

DE2_Basic_Computer\verilog\nios_system.ptf

DE2_Basic_Computer\verilog\nios_system.qip

DE2_Basic_Computer\verilog\nios_system.v

DE2_Basic_Computer\verilog\Onchip_memory.hex

DE2_Basic_Computer\verilog\Onchip_memory.v

DE2_Basic_Computer\verilog\Pushbuttons.v

DE2_Basic_Computer\verilog\Red_LEDs.v

DE2_Basic_Computer\verilog\sdram_test_component.v

DE2_Basic_Computer\verilog\Serial_port.v

DE2_Basic_Computer\verilog\Slider_switches.v

DE2_Basic_Computer\verilog\SRAM.v

DE2_Basic_Computer\verilog\sysid.v

DE2_Basic_Computer\vhdl

DE2_Basic_Computer\vhdl\Altera_UP_RS232_Counters.v

DE2_Basic_Computer\vhdl\Altera_UP_RS232_In_Deserializer.v

DE2_Basic_Computer\vhdl\Altera_UP_RS232_Out_Serializer.v