文件名称:FPGA-DSP

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2017-05-31
  • 文件大小:
  • 4.68mb
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  • 0次
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  • 何*
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FPGA数字信号处理实现原理及方法的例程-FPGA digital signal processing principle and method routines
(系统自动生成,下载前可以参看下载内容)

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FPGA鏁板瓧淇″彿澶勭悊瀹炵幇鍘熺悊鍙婃柟娉?

FPGA鏁板瓧淇″彿澶勭悊瀹炵幇鍘熺悊鍙婃柟娉?dsp48e_application

.............................................................\accumulator_96bit_tb.vhd

.............................................................\addaccum96.v

.............................................................\addaccum96.vhd

.............................................................\mult59x59.v

.............................................................\mult59x59.vhd

.............................................................\mult59x59_tb.v

.............................................................\PolyDecFilter.zip

.............................................................\PolyIntrpFilter.zip

.............................................................\README.txt

.............................................................\test

.............................................................\....\abs24_test.v

.............................................................\....\accum48_test.v

.............................................................\....\add4_46_test.v

.............................................................\....\addsub48_test.v

.............................................................\....\addsub96_test.v

.............................................................\....\autoreset_pd_test.v

.............................................................\....\barrelshifter_18bit_test.v

.............................................................\....\cntr_load_test.v

.............................................................\....\comp_mult_pipe_test.v

.............................................................\....\conv_round_cc_test.v

.............................................................\....\conv_round_lsb_test.v

.............................................................\....\div_mult_cascade_test.v

.............................................................\....\dsp_adder12_test.v

.............................................................\....\dsp_adder24_test.v

.............................................................\....\dsp_adder48_test.v

.............................................................\....\fast_sqrt_mult_cascade_test.v

.............................................................\....\logic48_test.v

.............................................................\....\macc18x18_test.v

.............................................................\....\mult25x18_parallel_pipe_test.v

.............................................................\....\mult25x35_parallel_pipe_test.v

.............................................................\....\mult35x35_parallel_pipe_test.v

.............................................................\....\mult35x35_sequential_pipe_test.v

.............................................................\....\mult_low_power_test.v

.............................................................\....\pattern_match_test.v

.............................................................\ucf

.............................................................\...\abs24.ucf

.............................................................\...\accum48.ucf

.............................................................\...\add4_46.ucf

.............................................................\...\addsub48.ucf

.............................................................\...\addsub96.ucf

.............................................................\...\autoreset_pd.ucf

.............................................................\...\barrelshifter_18bit.ucf

.............................................................\...\cntr_load.ucf

.............................................................\...\comp_mult_pipe.ucf

.............................................................\...\conv_round_cc.ucf

.............................................................\...\conv_round_lsb.ucf

.............................................................\...\div_mult_cascade.ucf

............................................

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