将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。
将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts.
A large operation is decomposed into a number of small operations, each small operation time is small, so can increase the frequency, each small operation can be executed in parallel, so can improve the data throughput rate.)相关搜索： verilog
pipeline