文件名称:No.201710061347=UART_Verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
1.硬件平台： FPGA；
2.编程语言： Verilog；
3.串口通信RS232的Verilog实现版本；(1. hardware platform: FPGA;
2. programming language: Verilog;
The Verilog implementation version of 3. serial port communication RS232;)
2.编程语言： Verilog；
3.串口通信RS232的Verilog实现版本；(1. hardware platform: FPGA;
2. programming language: Verilog;
The Verilog implementation version of 3. serial port communication RS232;)
相关搜索： FPGA串口通信
(系统自动生成,下载前可以参看下载内容)
下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| verilog-uart-master | 0 | 2016-09-13 |
| verilog-uart-master\.gitignore | 33 | 2016-09-13 |
| verilog-uart-master\.travis.yml | 426 | 2016-09-13 |
| verilog-uart-master\AUTHORS | 40 | 2016-09-13 |
| verilog-uart-master\COPYING | 1064 | 2016-09-13 |
| verilog-uart-master\README | 9 | 2016-09-13 |
| verilog-uart-master\README.md | 3592 | 2016-09-13 |
| verilog-uart-master\example | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\Makefile | 402 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\common | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\common\xilinx.mk | 6093 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\fpga.ucf | 12556 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\fpga\Makefile | 750 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\lib | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\lib\uart | 12 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl | 0 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl\debounce_switch.v | 2576 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl\fpga.v | 4379 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl\fpga_core.v | 3861 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl\sync_reset.v | 1615 | 2016-09-13 |
| verilog-uart-master\example\ATLYS\fpga\rtl\sync_signal.v | 1743 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\Makefile | 402 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\common | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\common\vivado.mk | 3758 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\fpga.xdc | 2212 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\fpga\Makefile | 509 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\lib | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\lib\uart | 12 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl | 0 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl\debounce_switch.v | 2576 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl\fpga.v | 4356 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl\fpga_core.v | 3431 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl\sync_reset.v | 1615 | 2016-09-13 |
| verilog-uart-master\example\NexysVideo\fpga\rtl\sync_signal.v | 1743 | 2016-09-13 |
| verilog-uart-master\example\VCU108 | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\Makefile | 402 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\common | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\common\vivado.mk | 3758 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\fpga.xdc | 3044 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\fpga | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\fpga\Makefile | 965 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\lib | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\lib\uart | 12 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl | 0 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl\debounce_switch.v | 2576 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl\fpga.v | 4798 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl\fpga_core.v | 3507 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl\sync_reset.v | 1615 | 2016-09-13 |
| verilog-uart-master\example\VCU108\fpga\rtl\sync_signal.v | 1743 | 2016-09-13 |
| verilog-uart-master\rtl | 0 | 2016-09-13 |
| verilog-uart-master\rtl\uart.v | 2851 | 2016-09-13 |
| verilog-uart-master\rtl\uart_rx.v | 4073 | 2016-09-13 |
| verilog-uart-master\rtl\uart_tx.v | 3129 | 2016-09-13 |
| verilog-uart-master\tb | 0 | 2016-09-13 |
| verilog-uart-master\tb\axis_ep.py | 14227 | 2016-09-13 |
| verilog-uart-master\tb\test_uart_rx.py | 4285 | 2016-09-13 |
| verilog-uart-master\tb\test_uart_rx.v | 2225 | 2016-09-13 |
| verilog-uart-master\tb\test_uart_tx.py | 4208 | 2016-09-13 |
| verilog-uart-master\tb\test_uart_tx.v | 2063 | 2016-09-13 |
| verilog-uart-master\tb\uart_ep.py | 5143 | 2016-09-13 |