文件名称:cpu_vhdl_vivado

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2017-11-29
  • 文件大小:
  • 1.2mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • dead*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

一个在fpga平台上的基本cpu的demo...........(A basic CPU demo on the FPGA platform...)
相关搜索: fpga

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
cpu_vhdl_vivado
cpu_vhdl_vivado\OpenHEC_user_cpu_1.0.zip 19624 2017-01-06
cpu_vhdl_vivado\component.xml 16295 2017-01-06
cpu_vhdl_vivado\cpu_src
cpu_vhdl_vivado\cpu_src\alu_74181.vhd 4627 2014-03-24
cpu_vhdl_vivado\cpu_src\alu_8.vhd 3026 2014-03-24
cpu_vhdl_vivado\cpu_src\clock_divider.vhd 1677 2014-03-24
cpu_vhdl_vivado\cpu_src\cpu.vhd 8740 2017-01-06
cpu_vhdl_vivado\cpu_src\data_bus.vhd 2645 2014-03-24
cpu_vhdl_vivado\cpu_src\four_one.vhd 1459 2014-03-24
cpu_vhdl_vivado\cpu_src\jqm_control.vhd 5157 2014-03-24
cpu_vhdl_vivado\cpu_src\mem_2.vhd 2224 2014-03-24
cpu_vhdl_vivado\cpu_src\mem_256x8.vhd 1626 2014-03-24
cpu_vhdl_vivado\cpu_src\pc.vhd 1539 2015-11-10
cpu_vhdl_vivado\cpu_src\reg_74244.vhd 1200 2014-03-24
cpu_vhdl_vivado\cpu_src\reg_74373.vhd 1414 2014-03-24
cpu_vhdl_vivado\cpu_src\reg_mine.vhd 1416 2014-03-24
cpu_vhdl_vivado\cpu_src\sim
cpu_vhdl_vivado\cpu_src\sim\clock_divider.vhd 1677 2014-03-24
cpu_vhdl_vivado\cpu_src\sim\cpu_test.vhd 2215 2017-01-06
cpu_vhdl_vivado\cpu_src\sim\ct.vhd 2229 2014-03-24
cpu_vhdl_vivado\cpu_src\sim\one_four.vhd 1501 2014-03-24
cpu_vhdl_vivado\cpu_src\sim\pc_test.vhd 2413 2014-03-24
cpu_vhdl_vivado\cpu_src\sim\reg_74377.vhd 1269 2014-03-24
cpu_vhdl_vivado\cpu_src\user_mux.vhd 1459 2014-03-24
cpu_vhdl_vivado\cpu_src\zl_divider.vhd 1321 2015-11-10
cpu_vhdl_vivado\cpu_src\zx_jh.vhd 4029 2015-11-10
cpu_vhdl_vivado\cpu_test_behav.wcfg 1318 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.cache
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt\java_command_handlers.wdf 154 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt\synthesis.wdf 3735 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt\synthesis_details.wdf 100 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt\webtalk_pa.xml 1417 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.cache\wt\xsim.wdf 256 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.hw
cpu_vhdl_vivado\cpu_vhdl_vivado.hw\cpu_vhdl_vivado.lpr 290 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\.jobs
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\.jobs\vrs_config_1.xml 240 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\.jobs\vrs_config_2.xml 228 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\.jobs\vrs_config_3.xml 210 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\.jobs\vrs_config_4.xml 210 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\dist_mem_gen_0_synth_1
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\.Vivado_Synthesis.queue.rst
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\.Xil
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\.vivado.begin.rst 175 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\.vivado.end.rst
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\ISEWrap.js 4766 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\ISEWrap.sh 1622 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\dont_touch.xdc 1013 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\gen_run.xml 2050 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\htr.txt 377 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\inst_rom.dcp 15959 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\inst_rom.tcl 3003 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\inst_rom.vds 39718 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\inst_rom_utilization_synth.pb 231 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\inst_rom_utilization_synth.rpt 6984 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\project.wdf 1840 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\rundef.js 1307 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\runme.bat 229 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\runme.log 40038 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\runme.sh 1136 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\vivado.jou 512 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\inst_rom_synth_1\vivado.pb 63035 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\.Vivado_Synthesis.queue.rst
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\.Xil
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\.vivado.begin.rst 175 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\.vivado.end.rst
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\ISEWrap.js 4766 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\ISEWrap.sh 1622 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\cpu.dcp 69866 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\cpu.tcl 1724 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\cpu.vds 30411 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\cpu_utilization_synth.pb 231 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\cpu_utilization_synth.rpt 7619 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\gen_run.xml 4606 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\htr.txt 367 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\project.wdf 1840 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\rundef.js 1297 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\runme.bat 229 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\runme.log 30719 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\runme.sh 1126 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\vivado.jou 484 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.runs\synth_1\vivado.pb 53813 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.sim
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\.Xil
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\.Xil\Webtalk-5080-WT430
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\.Xil\Webtalk-5080-WT430\webtalk
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\.Xil\Webtalk-7892-WT430
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\.Xil\Webtalk-7892-WT430\webtalk
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\compile.bat 410 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\compile.log 2503 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\cpu_test.tcl 460 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\cpu_test_behav.wdb 925280 2017-01-06
cpu_vhdl_vivado\cpu_vhdl_vivado.sim\sim_1\behav\cpu_test_vhdl.prj 932 2017-01-06

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